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Designs and tests next-generation RF integrated circuits for SpaceX’s Starlink satellite internet network, working with RF/analog/mixed-signal circuits in SiGe or CMOS processes.
Designs and tests next-generation RF integrated circuits for SpaceX’s Starlink satellite internet network, focusing on high-frequency analog and mixed-signal components in SiGe or CMOS processes.
SpaceX is hiring a physical design engineer to develop next-generation ASICs for the Starlink satellite and ground network. Day to day this means running synthesis, floorplanning, place-and-route, and timing/signoff closure (STA, noise, EM, IR drop), plus building physical-design automation scripts, using RTL2GDSII flows, EDA tools, and Python/TCL/Perl scripting.
SpaceX's Starlink team in Austin, TX is hiring a Physical Design Engineer to build next-generation ASICs for satellite and ground internet infrastructure. The role covers RTL-to-GDSII physical implementation — synthesis, floorplanning, place and route, and STA/signoff closure — plus developing physical design automation scripts (TCL, Python, Perl).
About the Role Hippocratic AI is seeking a Director, Product Marketing to own positioning, messaging, and go-to-market strategy for enterprise-grade agentic AI. You will translate complex technology into clear business…
Lumotive is pioneering the era of programmable optics—where light is controlled as intelligently and flexibly as software. At the heart of this transformation is a once-in-a-generation innovation: a flat CMOS-based…
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Join Hire Hangar and work with fast-growing global companies while building a long-term career. Role Overview We are seeking a driven Enterprise Account Executive to own and grow our Real Estate vertical. In this role,…
Are you a PLL Design Engineer passionate about developing the high-speed clocking technology that will power the next generation of AI infrastructure? Join our fast-growing semiconductor startup and help deliver…
Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation…
The Director, CMC-Drug Product Manufacturing, leads drug product manufacturing activities, overseeing external manufacturing, technology transfer, fill-finish, formulation development, analytical development, testing…
An internship at Apple in Munich writing software to improve hardware verification on upcoming Apple hardware products, combining traditional automation and EDA tools with emerging AI/ML techniques to build next-generation verification flows.
Businesses of all shapes and sizes rely on Google’s unparalleled advertising solutions to help them grow in today's dynamic marketing environment. You bring a passion for sales, knowledge of online media, and…
Valuates mortgage-backed securities and derivatives for a global hedge fund, ensuring accurate pricing and compliance with firm policies.
Company Overview Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold…
Renesas seeks a Senior Staff Analog Design Engineer in Chandler, AZ to provide technical leadership for complex power-management ICs and mixed-signal semiconductor products. Day to day, they lead analog subsystem architecture and CMOS circuit design from concept through silicon validation and production, drive design reviews, and mentor other engineers.
Renesas is hiring a Senior Analog Design Engineer in Chandler, AZ to own CMOS analog and mixed-signal circuit blocks (amplifiers, LDOs, references, oscillators, bias circuits) for power-management ICs from specification through silicon characterization and production. Core work centers on transistor-level design and simulation in the Cadence EDA environment, layout collaboration, and lab debugging
Staff-level analog IC design engineer at Renesas who technically owns major analog and power-management circuit blocks in PMIC and mixed-signal products, taking designs from architecture and feasibility through silicon validation and production. Hands-on CMOS transistor-level design, leading design reviews, and mentoring other analog engineers.
Each of us cares about someone who will need medicines. That’s why our vision is to repeatedly beat the odds to deliver breakthrough medicines to patients who need them. We pursue truth and scientific rigour and have…
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