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Design and implement FPGA firmware for surgical robotics using System Verilog, focusing on video processing, motor control, and high-speed comms, then integrate and validate the designs in Intuitive’s robotic systems.
Build ultra-low-latency FPGA/ASIC components for a global market-making engine, coding in SystemVerilog and Python and seeing designs run on real hardware.
We are looking for a Chip Design DFT/Post Silicon Manager to develop the next generation DFT technologies. As a Chip Design DFT/Post Silicon Manager in the DFT team at NVIDIA, you will lead team that transfer our DFT…
Lead FPGA design and hardware acceleration for low-latency trading systems, defining architectures for market connectivity and protocol processing to optimize performance and deterministic behavior.
Designs and maintains FPGA firmware, RTL modules, and device drivers while optimizing performance and debugging hardware-software integration for signal-processing systems.
Leads firmware development for FPGA-based systems, capturing requirements, designing and verifying hardware logic, and integrating with embedded software and PCB designs.
Designs and verifies digital logic for SoCs using VHDL/Verilog, ensuring low-power compliance and DFT readiness, with FPGA prototyping and silicon validation.
Design verification engineer building and running SystemVerilog/UVM testbenches for DDR5/LPDDR5 memory interfaces and DFI protocols in AMD’s server products.
Lead verification of DDR5/LPDDR5 memory interfaces for server chips using SystemVerilog, UVM, and C/C++; mentor engineers and align firmware/software with hardware features.
Design and verify next-gen FPGA devices using UVM, SystemVerilog, and AI/ML-enabled methodologies; collaborate with emulation and SoC teams.
Designs and implements ASIC chips in Verilog/SystemVerilog, closing timing/power goals and collaborating with verification and physical-design teams to bring silicon from RTL to production.
Intern designs FPGA-based embedded systems and writes low-level C code for Altera’s SoC devices, collaborating with hardware and software teams.
Design and optimize FPGA-based signal processing and embedded computing solutions for defense and aerospace, using RTL, DSP Builder, and embedded processors.
Design and implement high-performance FPGA logic for embedded machine-vision systems, including RTL coding, simulation, and vendor selection, while collaborating with hardware and software teams.
Design and integrate next-gen GPU hardware for mobile graphics, collaborating across teams to optimize power, performance, and area while ensuring high-quality delivery.
Designs and verifies high-performance FPGA subsystems for network test and measurement hardware using Verilog/SystemVerilog and industry-standard EDA tools.
Principal Engineer designing and verifying FPGA/ASIC solutions for Rolls-Royce engine control systems using VHDL/Verilog and DO-254 standards.
Design and optimize DRAM circuits (arrays, control logic, I/O) for next-gen memory chips, using Verilog, SPICE tools, and Python/Tcl, while leading tape-outs and mentoring engineers.
Senior engineer building and improving ASIC verification infrastructure, CI/CD flows, and AI-assisted debug tools for GPU development at NVIDIA.
Designs and reviews secure hardware/firmware architectures for semiconductors, including cryptography, side-channel analysis, and Verilog/C/C++ implementations.
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