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Designs and verifies digital semiconductor IP using Verilog/System Verilog, UVM, and Python/C++; performs CDC, DFT, and static timing checks; collaborates on verification test plans.
Designs and verifies semiconductor logic for communication chips using Verilog/SystemVerilog, CDC tools, and emulation platforms to ensure zero-defect silicon.
Firmware Engineer - National Security Business Be part of a growing and highly trusted supplier into the NS domain working to deliver mission critical solutions helping to keep the nation safe, secure and prosperous.…
Lead verification of DDR5/LPDDR5 memory interfaces for AMD server chips using SystemVerilog, UVM, and C/C++; mentor engineers and align firmware/software with hardware requirements.
Lead a team to design and deliver next-gen processor and SoC IP, driving RTL development, verification, and silicon execution while optimizing power, performance, and area.
Designs and implements high-performance processor cores and SoC subsystems using Verilog/SystemVerilog, driving microarchitecture, RTL, and PPA trade-offs with cross-functional teams.
Designs and verifies digital RTL subsystems for semiconductor products, using SystemVerilog/Verilog and collaborating with architecture and verification teams.
Design and implement embedded firmware for radar systems, integrating hardware/software components and accelerating algorithm development using C/C++, Python, and Xilinx tools.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Vil du være med til at udvikle næste generation af elektronikprodukter til højkvalitet lydproduktion inden for live musik, musikindspilning og filmproduktion applikationer? Vi søger: Hardware udvikler med fokus på…
Design Verification Engineer at AMD builds and runs SystemVerilog/UVM testbenches to validate DDR5, LPDDR5, and DFI memory interfaces for server products, collaborating with hardware, firmware, and software teams.
Designs ASIC microarchitectures using Verilog HDL, leads RTL architecture discussions, and ensures quality through synthesis, timing, and power analysis in hardware development.
Lead the architecture and validation of next-gen enterprise storage hardware, designing high-speed systems with x86, PCIe, and 800Gbps+ Ethernet while ensuring reliability through automated testing and signal-integrity analysis.
Design and develop embedded firmware for real-time control systems powering stellarator fusion devices, using FPGAs, PetaLinux, and hardware bring-up.
Designs and verifies mixed-signal ICs, building simulation environments and automated regressions to ensure silicon meets specs before tapeout and aligns with customer needs.
Intern designs FPGA/ASIC hardware for ultra-low-latency trading systems, writing RTL in SystemVerilog, verifying with vendor tools, and deploying to live silicon.
Design and verify FPGA-based hardware for Dolby’s cinema servers, audio processors, and HDR projection systems using VHDL/Verilog/SystemVerilog and advanced verification tools.
Principal Digital Engineer designs and implements DFT/Scan for automotive PMIC chips, working with RTL, synthesis, ATPG, and test teams to meet ASIL-B/D requirements and validate patterns on silicon.
Lead digital design for advanced RAIN RFID reader chips, owning RTL through tapeout and silicon validation while mentoring engineers and improving ASIC flows.
Build ultra-low-latency trading systems using FPGA hardware, VHDL/SystemVerilog, and Python/C++ in a fast-paced quantitative trading environment.
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