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Position Summary Maintains accurate financial records and supports close activities, reconciliations, reporting, bank audit readiness, and location-level analysis. The Assistant Controller converts vendor interactions…
A hands-on senior individual contributor who designs, builds, and maintains governed data models and ingestion pipelines in Snowflake, refactoring business logic out of Power BI datasets to power reporting across retail, cultivation, manufacturing, marketing, and finance at a cannabis company.
ABOUT BASETEN Baseten powers mission-critical inference for the world's most dynamic AI companies, like Cursor, Notion, OpenEvidence, Abridge, Clay, Gamma, and Writer. By uniting applied AI research, flexible…
About DHL Supply Chain: As the world’s largest contract logistics specialist, we create a competitive advantage for our customers by giving them logistics solutions based on our globally standardized warehousing,…
Marketingkoordinator (barselsvikariat) Er du stærk på digital marketing, content og koordinering, og vil du skabe målbare resultater? Så er det måske dig, vi leder efter. Hos ENVO IT hjælper vi virksomheder med at få…
About the Role The Major Account Executive is a high-impact, full-cycle sales role responsible for driving new customer revenue through strategic prospecting and disciplined execution. This is a true hunter position,…
Senior Project Manager at Inovalon (hybrid, Canonsburg, PA) who owns projects end to end — chartering, planning, tracking, stakeholder communication, risk management, and process improvement — while aligning business and technical teams in a healthcare data context, using MS Office 365 tools like MS Project, SharePoint, and Visio.
Inovalon, a healthcare data solutions company, is hiring a Senior Project Manager for a hybrid role in Canonsburg, PA (2 days/week onsite). The PM drives projects end to end — planning, tracking, stakeholder communication, risk management, and process improvement — working with cross-functional and technical teams using Microsoft Office 365 tools.
Designs and builds network automation and observability tooling for a global AI cloud platform, using Go/Python to make large-scale data center networks safe, scalable, and reliable.
Leads QA teams across the Americas to ensure medical-device quality compliance with ISO 13485, EU MDR, and FDA 21 CFR Part 820 while driving operational excellence and continuous improvement.
Leads finance and accounting for a growing IT services firm, handling day-to-day operations, strategic planning, and global financial management across the US, Canada, and India.
Applications will be accepted until 09:00am Thursday, September 17, 2026 At the core of Doctors Without Borders/Médecins Sans Frontières (MSF) Canada’s identity is a commitment to medical ethics, independence,…
Intern verifying RISC-V and AI accelerator SoCs using SystemVerilog, UVM, and Python to ensure functional correctness and robustness.
Develop scalable verification infrastructure and software for high-performance RISC-V CPUs using C++, Python, and SystemVerilog. Responsibilities include building testbenches, optimizing Verilog for simulation and FPGA emulation, and maintaining CI/CD pipelines.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
Leads a team of Verification Engineers to shape test strategies for AI hardware, validating functionality and performance of AI cores. Core technologies include AI-specific data types, compute patterns, on-chip network validation, UVM, SystemVerilog, and cocotb.
Full-chip physical design verification engineer ensuring manufacturable silicon for AI SoCs using DRC/LVS/ERC flows and advanced nodes (7nm–3nm).
Physical Design Engineer owning Die-to-Die interface implementation from RTL to GDSII for advanced-node chiplet architectures, using full PD flow (synthesis, P&R, CTS, sign-off) with Synopsys/Cadence/Mentor EDA tools and Tcl/Python automation.
Drive static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs, collaborating with logic, DFT, and physical design teams using STA tools, SDC constraints, and Python/Perl/TCL scripting.
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