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Build and deploy generative AI systems using LLMs, RAG, and agentic workflows; fine-tune models and evaluate performance for Qualcomm’s core AI products.
Lead the design of camera and image-processing ASIC IP blocks using RTL, synthesis, and PPA analysis, while driving GenAI tools for hardware workflows and agentic AI solutions.
Design physical layouts for SRAM and custom memory blocks using Cadence Virtuoso, verify with DRC/LVS, and collaborate with global teams to meet performance and manufacturability targets.
Develop and integrate embedded software for mobile chipsets, collaborating with cross-functional teams to debug, optimize build systems, and ensure performance and stability in C/C++/assembly.
Designs and optimizes SoC infrastructure IPs like interconnects, caches, and memory controllers for Qualcomm’s next-gen chips, balancing hardware-software trade-offs and collaborating with cross-functional teams.
Designs and implements CPU micro-architectures and RTL for high-performance, low-power chips, collaborating with architects and verification teams.
Designs and implements ASIC physical layouts for DSP cores used in mobile, compute, and AI products, handling floorplanning through tapeout.
Develops and optimizes ML/AI compilers and performance tools to efficiently map neural networks onto Qualcomm’s hardware, using C++, Python, and PyTorch.
Designs and optimizes high-speed VLSI chips, collaborating with architecture and verification teams to reduce power consumption and ensure quality.
Develops and maintains WLAN firmware and Linux drivers for Qualcomm’s wireless chips, focusing on IEEE 802.11 standards and RF integration.
Senior Staff Platform Engineer at Qualcomm in Bangalore developing BSP, drivers, and Autosar software for SoC hardware blocks like clocks, power management, and peripherals.
Develops and optimizes machine learning compiler tools and frameworks to enable efficient AI model deployment on Qualcomm hardware for mobile, edge, and IoT products.
Design and optimize CPU physical layouts using synthesis, place & route, and timing/power analysis to meet PPA targets for Qualcomm's next-gen processors.
Build and optimize Qualcomm’s AI Runtime SDK to deploy large generative models (LLMs, LVMs) efficiently on Snapdragon chips using C/C++ and Python.
Designs and documents high-speed PCB layouts for Qualcomm’s 5G platforms using Siemens Xpedition and Mentor tools, ensuring manufacturability and alignment with electrical/mechanical constraints.
Implementation Engineer, Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware…
Oversee multi-team programs for Qualcomm’s hardware products, coordinating schedules, budgets, and risks while aligning stakeholders across engineering and leadership.
Test engineer validating Wi-Fi features and AI/ML applications on embedded edge devices using Python automation and log analysis.
Develop embedded and cloud-edge networking software for wireless LAN solutions, focusing on packet flow, device drivers, and AI/ML-based traffic management using C/C++ and Linux kernel internals.
Designs and verifies high-speed interconnect protocols (PCIe, CXL, AXI) using UVM and SystemVerilog to ensure ASIC/subsystem correctness before tape-out.
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