Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Develops and maintains custom Linux images for autonomous systems hardware, including kernel customization, driver development, and hardware bring-up for GPS-denied environments.
Leads ROCm software validation for AMD’s AI/ML GPU platforms, defining test strategies, infrastructure, and release gates for multi-GPU/server workloads (e.g., LLMs, HPC). Owns end-to-end validation, debugs complex failures, and mentors engineers.
Role Overview We are seeking a highly experienced Design Verification Leader to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting AI,…
Position Overview As a Lead Hardware Engineer in our Systems Engineering group, you will be responsible for delivering systems and sub-assemblies, taking them from concept to production. These hardware designs…
Architects and implements structural test methodologies for AMD’s Instinct Accelerator hardware, debugging SMT/PCB/component issues and optimizing test coverage from EVT to mass production.
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Develops and maintains emulation infrastructure for Google Cloud’s TPU hardware, focusing on verifying complex digital designs and debugging emulation platforms to accelerate AI/ML hardware acceleration.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Designs and validates power delivery networks for AMD’s high-performance GPU platforms, ensuring efficient and reliable power conversion for CPUs/GPUs/APUs in data center environments.
Leads verification of complex SoC subsystems (e.g., memory/cache, coherency, PCIe/DDR) using UVM/SystemVerilog, ensuring functionality, performance, and security. Owns test strategy, debugging, and cross-team collaboration for sign-off.
Designs and owns RTL blocks for SambaNova’s AI-accelerating RDU ASICs, shepherding them from spec to silicon bring-up while optimizing for power, performance, and area.
Builds and maintains hardware emulation models for SambaNova’s AI workload accelerator (RDU), enabling pre-silicon software bring-up, performance verification, and verification acceleration. Works with RTL teams to ensure emulation-readiness, owns platform automation, and advises cross-functional teams on emulation strategy.
【Background of the Recruitment】 As automotive electrification and intelligence continue to accelerate, automotive SoCs have become a core technology that directly influences vehicle value. The R-Car series has evolved…
【募集背景】 自動車の電動化・知能化が急速に進む中、車載SoCはクルマの価値を左右する中核技術となっています。 R-Carシリーズは、CPU、高速インタフェース、メモリ、AI／ビデオ、機能安全、セキュリティなど、多数のSoC IPを高度に統合した、大規模かつ高機能な車載SoCとして進化を続けてきました。 当部門では、こうした次世代車載SoCの開発を継続的に推進するため、自社IP開発に加え、導入IPの選定・組み込みを含めたSoC…
The role develops and integrates PCIe-related IP blocks, evaluates performance, supports verification closure and functional coverage, debugs pre-silicon and post-silicon issues, and contributes to software development…
Designs and owns a high-throughput data pipeline for a diagnostic instrument platform, handling real-time image acquisition, GPU-accelerated signal processing, and distributed HPC/cloud processing with reliability and scalability.
About Majestic Labs We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it…
Engineer hardware platforms for LTE/5G base stations using SDR and OpenRAN, handling server diagnostics, Linux administration, and vendor interactions in a startup-like corporate environment.
Lead physical design (RTL-to-GDS) for AMD’s next-gen AI and high-performance ASICs, driving PnR, timing closure, and tape-outs while collaborating with architects and EDA vendors.
We couldn't check your fit for this role — add a CV to your profile to see it next time.