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Tech Lead Design Engineer Location: San Jose, California, United States Department: Board Validation Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By…
Designs and verifies RTL for AI NPUs, focusing on SoC blocks like interfaces, power management, and clocking using Verilog/SystemVerilog and scripting (Python/Tcl).
Contract FPGA engineers to design and implement Verilog/VHDL for satellite telecoms projects using Xilinx ISE and SystemVerilog.
Senior RF Systems Engineer designs and tests next-generation electronic warfare and drone-detection platforms, using SDR, signal processing, and RF hardware across 300–600 MHz, 2.4 GHz, and 5.8 GHz bands.
Application Engineer I: Systems Verification - Emulation Location: BELO HORIZONTE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of…
Design and implement FPGA-based digital logic using VHDL/Verilog, integrate custom IP cores, and optimize designs for performance and timing closure.
Senior Hardware Engineer designs and validates sports-tech hardware (PCBs, RF, FPGA) to ensure measurement accuracy and reliability for global athletes.
Designs and automates ASIC front-end methodologies for IP/SoC projects, using EDA tools like SpyGlass and scripting in Python/Perl/TCL to improve design checks and integration flows.
Design and verify complex silicon subsystems for Arm-based platforms using SystemVerilog/UVM, ensuring functionality, performance, and coverage closure.
Designs and verifies digital circuits for IoT and automotive chips using VHDL/Verilog, SystemVerilog, and Python, with a focus on signal processing and embedded software integration.
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
Graduate trainee develops FPGA IP cores using HDL, RTL design, and verification, working with tools like Vivado/Quartus and collaborating on real-world FPGA-based system projects.
Designs and optimizes system-on-chip (SOC) architectures for communication and multimedia products, defining hardware specs and signal-processing algorithms while leading cross-team collaboration.
Designs and debugs FPGA firmware, PCB schematics, and calibration tools for security systems like car park and airport detectors.
Build Python automation tools, dashboards, and AI-assisted workflows for semiconductor test development, then validate and analyze results to improve efficiency.
Design and verify FPGA-based systems using VHDL/SystemVerilog for aerospace/defense applications, collaborating with hardware and systems teams to meet DoD requirements.
Define next-gen NIC and DPU chip architectures for NVIDIA’s networking unit, collaborating with GPU/CPU teams to optimize performance and debug full-chip correctness issues.
Design-for-Test engineer implementing scan, MBIST, JTAG, and ATPG flows to improve SoC test coverage and silicon yield while collaborating with cross-functional teams.
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Lead a team designing and implementing next-generation networking ASICs, guiding RTL development, implementation, and tapeout while collaborating with cross-functional teams to meet performance and schedule targets.
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