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Lead CMOS analog/mixed-signal circuit design for SiTime's MEMS-based precision timing chips in Munich: define architectures, do transistor-level design and simulation of blocks like Frac-N PLLs, ADCs/DACs and regulators, supervise analog designers and layout, and drive silicon bring-up and validation across PVT.
Roles & Responsibilities JOB RESPONSIBILITIES / AUTHORIZATION LEVEL Innovate and Create value for Next Generation of advanced complex system. and design electronics architecture, circuits, and systems for meeting…
Electrical Engineer 4 Description: Join our fast-paced and passionate team as an Electrical Engineer 4. As we scale, you will be instrumental in building our foundation from the ground up. This is a dynamic, hands-on…
About Castelion Castelion is redefining defense development through rapid iteration, aggressive testing, and modern commercial manufacturing at scale. We design, build, and test next-generation long-range strike weapon…
Build the Electrical Systems Behind the Next Generation of Robotics We’re partnering with a high-growth robotics AI company building technology designed to fundamentally change how robots operate across real-world…
A pre-sales Senior Solution Consultant for Razor Labs' DataMind AI predictive maintenance platform, working with mining clients across Australia. Day to day: lead technical discovery with reliability and operations teams, run proof-of-value projects, deliver demos and proposals, and support implementation until customer KPIs are met. Requires hands-on mining, sensor/instrumentation and analytics e
ABOUT OUR MISSION: Optics 1 is a global leader in full-service design and production of electro-optic and navigation systems. Leveraging core competencies in defense technologies, Optics 1 provides unmatched,…
Job Summary: T3i builds mission-critical unmanned systems designed to improve US forces operational and lethal capabilities on the battlefield. Our Blackfoot platform is a tactical FPV drone system engineered for…
Job Summary : We are seeking a PCB Design Engineer to serve as a primary resource for printed circuit board design and layout within our product development team. The successful candidate will own PCB layout activities…
Hardware Engineer specializing in RTL/PD, optimizing designs from microarchitecture to tapeout for AI-native ASICs at Normal Computing, a deep-tech semiconductor startup.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Lead hardware NPI programs at Astera Labs from design release through PCBA builds, validation, manufacturing readiness, and launch of connectivity hardware for rack-scale AI infrastructure. The role is cross-functional program management across hardware, systems, supply chain, quality, and contract manufacturers, grounded in PCB/PCBA expertise.
Principal Analog Design Engineer who architects and designs high-speed analog/mixed-signal circuits (PLLs, SerDes building blocks, ADCs/DACs, references, clocking) for Astera Labs' AI connectivity silicon, owning designs from spec through layout and silicon bring-up in advanced FinFET nodes, using Cadence Virtuoso/Spectre and mentoring the analog team.
Leads day-to-day DFT architecture and execution for Astera Labs' high-speed PCIe and Ethernet signal-conditioning chips used in rack-scale AI infrastructure. Day to day: defining test strategies (scan, ATPG, MBIST, JTAG), driving tape-out and production ramp, improving yield and diagnostics, and mentoring DFT engineers.
Lead R&D for advanced packaging of optical chips (NPO/CPO) for AI infrastructure, defining 2.5D/3D process flows, materials, and PDKs while driving yield and reliability improvements.
Hands-on principal-level analog IC designer at Astera Labs who architects high-speed analog/mixed-signal circuits (PLLs, SerDes, ADCs/DACs, clocking) for AI infrastructure connectivity silicon in advanced FinFET nodes, owning designs from spec through silicon bring-up while setting methodology and mentoring the analog team in San Jose.
Develops and debugs firmware for Ethernet retimers in AI infrastructure, troubleshooting link failures and integrating new products from silicon bringup to deployment.
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