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Senior Software Engineer, Compute Platform Integration
Own the embedded Linux boot chain and device tree for NVIDIA Jetson-based defense systems, ensuring hardware boots correctly and peripherals enumerate reliably in NixOS deployments.
Software Engineer, Tracking
Software engineer on Anduril's Air & Missile Defense Radar team who designs and implements real-time multi-target tracking algorithms and high-performance systems that process radar sensor data to detect and track airborne threats. Core stack is C++ and Python with strong math foundations; a U.S. Top Secret SCI clearance (or eligibility) is required.
Program Manager, JIATF
Program Manager to drive emerging defense tech initiatives, turning proposals into successful programs while managing cost, schedule, and performance for Air Defense’s strategic priorities.
Staff AI Infrastructure Engineer
Architect and scale the ML platform for autonomous defense systems, building training, orchestration, and serving infrastructure for AI models like LLMs and computer vision in cloud and air-gapped edge environments.
FPGA Verification Engineer, Air Dominance and Strike
Own verification of FPGA/SoC designs for flight-critical avionics using SystemVerilog and UVM methodology on AMD (Xilinx) platforms.
Senior System Engineer, ModSim, Joint Simulation Environment (JSE)
Senior systems engineer on Anduril's autonomy programs who builds and red-teams models and simulations (AFSIM/JSE), owns systems-level requirements, and produces MBSE artifacts (SysML/DoDAF/UAF in Cameo MagicDraw) supporting development, integration, and test of advanced mission autonomy systems.
System Engineer, ModSim, Joint Simulation Environment (JSE)
Systems engineer on Anduril's digital engineering team supporting autonomous airpower systems: building models and simulations in MODSIM environments (AFSIM/JSE), red-teaming designs, and producing MBSE and requirements-based testing artifacts. Requires an active U.S. Top Secret clearance.
Staff PCB Design Engineer
Designs and leads PCB layouts for defense tech, applying IPC standards and high-reliability practices in Altium Designer.