Tech jobs

Senior Mixed Signal Circuit Design Engineer

North AmericaSenior

AI Cmos MATLAB Signal Integrity Verilog

We are now looking for a Senior Mixed Signal Design Engineer to be part of the Mixed Signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic,…

NVIDIA

AI Asic Automation Bash GDB +4 skills

ASIC Design Engineer - Performance Monitoring

APAC

India

NVIDIA System-On-Chip (SOC) group is hiring for an ASIC Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet…

Nokia

On-siteNorth AmericaInternship H-1B sponsor history

Hardware Development Co-Op

FPGA Oscilloscope Pcb SystemVerilog Verilog +1 skills

Position: Hardware Development Co-op Number of Positions: 1 Duration: 8 months Term: January – August 2027 Location: Murray Hill, NJ (Onsite) Educational Recommendations Currently pursuing a Bachelor’s degree in…

Hewlett Packard Enterprise

North AmericaInternshipIntern Ireland permit employer

VLSI Logic Design Intern

Accessibility Backbone.js Cloud C++ Ethernet +9 skills

VLSI Logic Design InternThis role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud…

Hewlett Packard Enterprise

North AmericaInternshipIntern Ireland permit employer

VLSI Design Verification Intern

Accessibility Agentic AI AI Asic Automation +11 skills

VLSI Design Verification InternThis role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global…

Synopsys

Agentic AI AI Asic FPGA Pre-sales +7 skills

Applications Engineering, Architect - 19218

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…

祥碩科技股份有限公司

數位訊號處理演算法工程師(DSP)

APACFull-time

Taiwan

1. 與演算法團隊合作，分析 DSP 演算法之數學模型與運算需求。 2. 根據效能、面積與功耗需求，設計對應的數位硬體架構。 3. 使用 Verilog 撰寫 RTL 程式碼，實現演算法硬體化。 4. 撰寫 testbench 並進行功能模擬與驗證 (Functional Simulation / Verification)。 5. 支援ASIC synthesis、timing closure 相關工作。 6.…

Verilog

群創光電股份有限公司

FPGA I2c UART Verilog VHDL

X-ray_FPGA工程師(台南)

APACFull-time

Taiwan

1. 使用 Verilog / VHDL 進行 FPGA 邏輯設計與開發, IR-Sensor與高速資料的擷取與處理 2. 實作與整合通訊介面（SPI / I2C / UART / LVDS 等） 3. 進行時序分析與優化（Timing Closure） 4. FPGA 系統除錯與驗證（使用示波器、邏輯分析儀、SignalTap / ILA） 5. 撰寫測試平台（Testbench）與執行模擬驗證（ModelSim / Questa）

Raytheon

Open 15d On-siteNorth AmericaPrincipal

Principal Real-time Software Engineer

Agile Assembly C++ Embedded Software Firmware +8 skills

Principal embedded real-time software engineer at Raytheon (RTX) in Tucson, AZ, architecting, designing, implementing, and testing embedded real-time software within heterogeneous systems of firmware (FPGA) and hardware for autonomous avionics in defense systems. Core tech includes Embedded C++, RTOS platforms (VxWorks, Integrity, Linux), and hardware/firmware integration. Onsite role requiring an

108K – 205K $

Nuvoton Technology Corporation

Embedded Systems Ethernet FPGA Microcontrollers Oscilloscope +3 skills

Hardware Application Engineer

Open 54d HybridMENA

Israel

Hardware application engineer at Nuvoton Israel, a semiconductor design center supplying manageability and security microcontrollers (BMC, EC, SIO, TPM) to tier-1 computing/server OEMs. Day to day: guide customers through board/system design cycles, debug hardware issues hands-on, write reference schematics and app notes, and feed input into next-gen IC definitions.

The MITRE Corporation

Open 15d North AmericaInternshipSenior

Senior Embedded Security Engineer - Digital Systems Security

Asic C++ Cybersecurity Embedded Systems FPGA +6 skills

Senior hands-on R&D role in MITRE's Electronic Systems Security department: research secure design countermeasures, build FPGA hardware/software prototypes, and perform implementation attacks (side-channel, fault injection, microprobing) on embedded systems for U.S. government sponsors. Key tech: Verilog/VHDL, FPGA, Python/C++/Rust, crypto, secure boot. Onsite in Tysons Corner; Secret clearance re

127K – 190K $

Luxoft

APAC Licensed NL sponsor H-1B sponsor history

Firmware Engineer

India

Project description This is a great opportunity to work as part of a highly regarded team to deliver leading-edge solutions. Responsibilities Verifies power-management firmware rather than writing it: writes test…

C++ Firmware Python RTOS Verilog

Green Key Resources

Embedded Software Engineer

Open 16d North America

AI Bash C++ Embedded Systems Firmware +7 skills

Designs, integrates, and validates systems that combine custom electronics, FPGA/digital logic, embedded firmware, Linux, and application-level software across the full product lifecycle, from hardware bring-up through manufacturing and deployment. Core stack: C/C++, Python, Bash, Linux, Verilog/VHDL.

Perceptive Innovations

Open 16d North AmericaLead

Embedded Software Engineer

CUDA Embedded Linux Embedded Software FPGA GPU +16 skills

Leads embedded software architecture and development for FPGA SoC and CPU SoC systems — image processing for a battery-powered night vision goggle system, wideband RF signal processing, and synthetic aperture radar. Core stack: Xilinx FPGAs (Vivado/Vitis), embedded Linux/Yocto, CUDA on NVIDIA Jetson, and real-time Arm multicore development.

SpaceX

Open 17d North AmericaFull-time

ASIC Design Engineer (Silicon Engineering)

Asic Bash C++ Firmware FPGA +7 skills

Designs next-generation ASICs and FPGAs for SpaceX's Starlink satellites and ground infrastructure: RTL design and SoC integration in SystemVerilog/Verilog, power-performance-area optimization, participation in the full design lifecycle, and lab bring-up/validation, collaborating with systems, firmware, architecture, and backend teams.

135K – 210K $

ams OSRAM

Cmos PCIe Rtl SystemVerilog Verilog

Principal HS Digital Design Engineer (d/m/f)

Open 54d EuropePrincipal

Italy

Principal high-speed digital design engineer at ams OSRAM in Pavia, Italy, working on digital IC design for communication and mixed-signal SoC products: RTL design in Verilog/SystemVerilog, synthesis, timing analysis, clock-domain crossing, and advanced CMOS nodes (FinFET/FD-SOI). Knowledge of UCIe/PCIe interfaces is an advantage.

Capgemini

AI Embedded Systems Generative AI Iso 26262 Rtl +3 skills

VLSI Safety Architect

Open 43d HybridEurope

Serbia

Senior RTL/SoC Functional Safety engineer at Capgemini Engineering in Belgrade: designs hardware in Verilog/SystemVerilog, integrates ISO 26262 safety mechanisms and internal/third-party IPs into complex SoCs, and documents safety requirements through silicon delivery.

Capgemini

AI Automation Cloud Generative AI Perl +5 skills

Senior RTL Design Engineer

Open 43d CISSenior

Ukraine

Capgemini Engineering in Kyiv is hiring a Senior RTL Design Engineer with 8+ years of VLSI experience to design and verify complex digital SoC blocks — writing RTL in Verilog/SystemVerilog or VHDL, running CDC/RDC and lint analysis with Synopsys VC Static, and driving designs from specification through tape-out alongside synthesis, STA, and verification teams.

Capgemini