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Pre-Silicon Validation Engineer Location: India Department: Weekday's Client via platform Workplace: remote Employment Type: full Description This role is for one of the Weekday's clients Min Experience: 6+…
Designs and verifies RTL for AI accelerators and ASICs, optimizing hardware for machine-learning workloads.
Design Verification Engineer at Weekday AI: builds and validates AI hardware designs to ensure correctness and performance before tape-out.
Разработка прошивок для ПЛИС Intel на SystemVerilog/Verilog/VHDL и цифровых электрических схем, включая поддержку серийных проектов.
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route market data efficiently.
Build and optimize Bazel-based monorepo workflows for AI accelerator software/hardware, scaling CI/CD and developer tooling across Linux, macOS, and custom hardware.
Design and own full-chip mixed-signal CMOS behavioural models in Verilog-A/AMS for cryogenic quantum processors, enabling accurate simulation and tapeout decisions in IonQ’s Oxford lab.
Job Description: Passionate in analyzing performance bottlenecks and driving architectural improvements? Eager to expand into building SoC platforms for performance verification analysis? Arm’s System-on-Chip (SoC)…
Intern designs and verifies low-power digital ICs using SystemVerilog/Verilog, simulates MCUs, and prototypes designs on FPGA.
Build and validate new features for Jasper, a leading formal verification tool, using C++ and advanced algorithms and graph modeling.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems Inc. is looking for a motivated Application Engineer I: Systems Verification -…
Design and implement FPGA-based digital logic using VHDL/Verilog, verify designs, and optimize for performance and power in a high-tech hardware environment.
Design and verify ASIC/FPGA logic for high-speed networking hardware using Verilog/SystemVerilog, and collaborate on bring-up and validation.
Lead the full lifecycle of NVIDIA’s next-gen switch ASICs, coordinating RTL design, verification, physical design, and post-silicon bring-up with cross-functional teams.
Designs and implements reusable digital IP blocks (Verilog/SystemVerilog) for low-power wireless SoCs, focusing on PPA targets and AMBA/peripheral IP like SPI, UART, and DMA.
Designs and verifies System-on-Chip (SoC) subsystems using Verilog/SystemVerilog, integrating high-speed IPs like PCIe and DDR, and collaborating with verification and backend teams.
Design and verify mixed-signal ASICs and ROICs for image sensors, including analog signal chains, low-power ADCs, and system-level simulations using Cadence, MATLAB, and Python.
Lead mixed-signal IC design for advanced image sensors, guiding teams through full ASIC/ROIC development from architecture to validation in a hybrid role.
Job Summary The Electronics Design Engineer will work with the software manager to advance the Vertiv management platforms by: Creating technical documentation leading to physical electronic hardware Develop design…
Design AI/ML-driven automation for ASIC chip development, using GenAI, reinforcement learning, and neural networks to optimize power, performance, and area for NXP’s processors.
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