Tech jobs

Open 16d North AmericaLead

Embedded Software Engineer

CUDA Embedded Linux Embedded Software FPGA GPU +16 skills

Leads embedded software architecture and development for FPGA SoC and CPU SoC systems — image processing for a battery-powered night vision goggle system, wideband RF signal processing, and synthetic aperture radar. Core stack: Xilinx FPGAs (Vivado/Vitis), embedded Linux/Yocto, CUDA on NVIDIA Jetson, and real-time Arm multicore development.

SpaceX

Open 17d North AmericaFull-time

ASIC Design Engineer (Silicon Engineering)

Asic Bash C++ Firmware FPGA +7 skills

Designs next-generation ASICs and FPGAs for SpaceX's Starlink satellites and ground infrastructure: RTL design and SoC integration in SystemVerilog/Verilog, power-performance-area optimization, participation in the full design lifecycle, and lab bring-up/validation, collaborating with systems, firmware, architecture, and backend teams.

135K – 210K $

ams OSRAM

Cmos PCIe Rtl SystemVerilog Verilog

Principal HS Digital Design Engineer (d/m/f)

Open 54d EuropePrincipal

Italy

Principal high-speed digital design engineer at ams OSRAM in Pavia, Italy, working on digital IC design for communication and mixed-signal SoC products: RTL design in Verilog/SystemVerilog, synthesis, timing analysis, clock-domain crossing, and advanced CMOS nodes (FinFET/FD-SOI). Knowledge of UCIe/PCIe interfaces is an advantage.

AI Embedded Systems Generative AI Iso 26262 Rtl +3 skills

VLSI Safety Architect

Open 43d HybridEurope

Serbia

Senior RTL/SoC Functional Safety engineer at Capgemini Engineering in Belgrade: designs hardware in Verilog/SystemVerilog, integrates ISO 26262 safety mechanisms and internal/third-party IPs into complex SoCs, and documents safety requirements through silicon delivery.

AI Automation Cloud Generative AI Perl +5 skills

Senior RTL Design Engineer

Open 43d CISSenior

Ukraine

Capgemini Engineering in Kyiv is hiring a Senior RTL Design Engineer with 8+ years of VLSI experience to design and verify complex digital SoC blocks — writing RTL in Verilog/SystemVerilog or VHDL, running CDC/RDC and lint analysis with Synopsys VC Static, and driving designs from specification through tape-out alongside synthesis, STA, and verification teams.

FPGA GPU Iso 26262 Verilog VHDL

Capgemini Engineering Ingénieure/Ingénieur RTL design

Open 43d Europe

France

Capgemini Engineering is hiring an ASIC front-end RTL design engineer in Montbonnot-St-Martin, France, to specify, design (Verilog/SVerilog/VHDL), and integrate digital or mixed-signal IP into client SoCs, following DFT, CDC, RDC, Lint, and UPF rules alongside VLSI teams.

Agile AI Cloud FPGA Signal Processing +3 skills

FPGA Engineer

Open 43d EuropeLead

Italy

FPGA Engineer at Capgemini Engineering in Rome (onsite) who designs and develops FPGA-based hardware solutions for complex, high-performance projects — mainly for aerospace and defense clients — using VHDL, Verilog and SystemVerilog, implementing signal-processing algorithms, optimizing synthesis/place & route, and building testbenches for verification.

31K – 57K €

AI Embedded Systems Generative AI Iso 26262 Rtl +3 skills

VLSI Safety Architect

Open 43d HybridEurope

Greece

Senior RTL/SoC Functional Safety Engineer at Capgemini in Thessaloniki (Greece) who designs and integrates safety mechanisms into complex ASIC/SoC hardware in compliance with ISO 26262. Day-to-day work centers on RTL design in Verilog/SystemVerilog, configuring and integrating IPs, writing safety/integration documentation, and supporting SoC architecture and silicon delivery.

Rtl SystemVerilog Verilog VHDL

Senior Digital Designer

Open 43d EuropeSenior

Greece

Capgemini is hiring a Senior Digital Designer in Athens to lead functional specification development, microarchitecture, and RTL debugging for high-performance digital/semiconductor blocks, including lint and CDC checks. Core technologies: Verilog/VHDL, SystemVerilog, and synthesis tools like Cadence Genus and Synopsys Design Compiler.

FPGA GPU Iso 26262 Verilog VHDL

Expert RTL Design

Open 43d Europe

France

Capgemini Engineering is hiring a front-end ASIC RTL design expert in Montbonnot-Saint-Martin (Grenoble area, France) to specify, design, and debug digital and mixed-signal IPs in Verilog/SystemVerilog/VHDL, following DFT, CDC, RDC, Lint, and UPF rules, and to integrate them into SoC partitions alongside VLSI teams on advanced semiconductor products for clients.

AI Asic Automation Cloud Data Science +5 skills

RTL Design & IP Release Engineer

Open 20d Europe

Romania

Supports semiconductor Foundation IP development at Capgemini Engineering in Brasov, Romania: implementing and validating RTL Verilog design changes, running QA checks, and managing ClearCase-based IP release flows with Python automation. Core tech: Verilog/SystemVerilog, ASIC design, CDC/Lint, AMBA protocols, Linux.

Altera Corporation

Full Chip Timing Modeling and Integration Engineer

Open 15d North America

AI Automation FPGA Machine Learning PCIe +3 skills

Develops timing methodologies and performs hands-on full-chip static timing analysis for Altera's next-generation FPGAs on advanced process nodes — building, integrating, and validating high-level timing models with cross-functional, multi-site design teams. Core stack: STA, Liberty/Verilog/SDC, SPICE correlation, Python/Tcl, LVF/POCV.

133K – 193K $

jobs.atos.net

Data Science FPGA Git HPC Python +4 skills

Expert design logic ASIC H/F

Internship

Bull c’est une histoire. Un siècle d’innovation Européenne et un environnement de travail où des experts conçoivent des solutions numériques puissantes, durables et souveraines, permettant aux États et aux industries…

jobs.atos.net

Ethernet FPGA Linux PCIe Verilog +1 skills

Ingénieur développement FPGA Senior H/F

Senior

Bienvenue chez Eviden, là où l’avenir du numérique prend vie ! Avec 1 milliard d’euros de chiffre d’affaires annuel, Eviden est la branche du Groupe Atos pour les produits logiciels et matériels. Acteur clé de la tech…

opportunities.lamresearch.com

Altium C Embedded Linux Embedded Systems EtherCAT +11 skills

Embedded Systems Engineer 2

Hybrid

The group you’ll be a part of In the Global Products Group, we are dedicated to excellence in the design and engineering of Lam's etch and deposition products. We drive innovation to ensure our cutting-edge solutions…

career.karlstorz.com

AI Embedded Software FPGA GPU Image Processing +5 skills

FPGA Engineer IV

About the Role At KARL STORZ, the FPGA Design Engineer IV is responsible for designing, developing, testing, integrating, and verifying FPGA-based and accelerated imaging solutions for advanced medical video camera…

Arista Networks

Open 17d HybridNorth America Licensed UK sponsor Canada LMIA employer Ireland permit employer

FPGA Design Engineer

AI Arista Automation Bash Ethernet +11 skills

Designs and verifies control-path FPGA RTL (Verilog/SystemVerilog) for Arista's data center Ethernet switch platforms, owning the full lifecycle from architecture and board review through synthesis, timing closure, verification, and lab bring-up in collaboration with hardware, software, and manufacturing teams.

Arista Networks

Open 17d HybridNorth America Licensed UK sponsor Canada LMIA employer Ireland permit employer

FPGA Design Engineer

AI Arista Automation Bash Ethernet +11 skills

Design and verify high-performance control-path FPGAs for Arista's data center Ethernet switch platforms, owning the full lifecycle from Verilog/SystemVerilog RTL development and verification through synthesis, timing closure, and system bring-up. On-site role in Santa Clara, CA requiring 5+ years of RTL design experience.

110K – 170K $

Advanced Micro Devices, Inc