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Lead the design of camera and image-processing ASIC IP blocks using RTL, synthesis, and PPA analysis, while driving GenAI tools for hardware workflows and agentic AI solutions.
Designs and implements CPU micro-architectures and RTL for high-performance, low-power chips, collaborating with architects and verification teams.
Designs and implements ASIC physical layouts for DSP cores used in mobile, compute, and AI products, handling floorplanning through tapeout.
Designs and verifies high-speed interconnect protocols (PCIe, CXL, AXI) using UVM and SystemVerilog to ensure ASIC/subsystem correctness before tape-out.
Designs and verifies mixed-signal power-management ICs for compute, data center, automotive, and industrial systems using Cadence, Spectre, MATLAB, and Verilog/AMS.
Senior ASIC Implementation Engineer, Low Power AI Location: Markham, Ontario, Canada Department: ASICS Engineering Work Location: onsite Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group >…
Designs and optimizes System-on-Chip (SoC) architectures for mobile/IoT/XR platforms, focusing on performance, power, and security trade-offs.
Designs and implements mixed-signal IP blocks (DDR, USB, PCI, PLL) using nanometer technologies, focusing on physical design flow, timing closure, and verification to tape out high-quality silicon.
Design Verification Engineer at Qualcomm verifies Bluetooth chipset designs using SystemVerilog/UVM, formal checks, and emulation to ensure hardware meets specifications before production.
Design and implement CPU microarchitecture and RTL for high-performance, low-power devices, collaborating with architects and verification teams.
Job Details: Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled team developing cutting-edge silicon for GenAI workloads, where we push the…
Designs and verifies analog and mixed-signal ICs to emulate obsolete microcircuits for defense systems, using tools like Verilog/VHDL and Python.
Develop embedded C/C++ firmware and FPGA-based (Verilog) designs for microprocessor-based power-grid controls, optimizing for low-power and high-throughput data.
Design and verify FPGA-based prototypes for Intel’s IP blocks, integrating and debugging RTL designs to enable early hardware and software validation.
Develop and maintain hardware emulation platforms for ASIC/SoC designs, integrating and debugging RTL in emulation environments to enable pre-silicon validation.
Lead verification of complex SoC designs using SystemVerilog, UVM, and formal tools; mentor teams and drive coverage closure for memory-IP projects.
Leads verification of complex NAND memory IP blocks using SystemVerilog, UVM, and formal tools, mentors engineers, and drives silicon success for a flash-memory product company.
Design and implement a high-performance, low-power ASIC accelerator for AI inference, integrating CPU and custom IP blocks using Verilog/SystemVerilog and AMBA protocols.
Designs ultra-low-latency FPGA-based systems for real-time trading acceleration using RTL and hardware design, working alongside experts in a research-driven finance firm.
Architect next-generation pre-silicon verification strategies for complex semiconductor designs, leading simulation, formal, and emulation methodologies to ensure first-pass silicon success.
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