Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Cyber Defense Infrastructure Support Engineer Location: Suitland, MD Clearance: Active TS/SCI Join a mission focused team supporting the Navy’s cybersecurity environment at the ONI Hopper Global Communications Center!…
Monitor and investigate cybersecurity alerts on TS/SCI Navy networks, perform threat hunting, and manage incident tickets using SIEM platforms like Splunk and Elastic along with NIDPS and host-based security tools.
Develop and maintain FAA air traffic control software (primarily Ada95/C++) on UNIX/Linux platforms for the ERAM system, with support scripting in PERL/PYTHON, working on high-availability, real-time, multi-threaded systems.
Design, develop, and test software for space systems at Sierra Space, leading an engineering team and making high-level architectural decisions using Python, C++, and cloud/container technologies.
Hands-on IT Security Engineer focused on incident response, digital forensics, and security monitoring across a large university environment, using endpoint, network, and log data to investigate and contain threats.
Build, operate, and support DAP Middleware and PaaS platform services across on-prem and cloud environments, focusing on middleware technologies (Tomcat, JBoss, WebLogic), automation scripting in Python/Perl, and Splunk-based log analytics.
Ready to join the fast-paced world of navigating the shifting landscape of regulations for cryptocurrency and DeFi? We’re looking for an experienced Technical Support Engineer to join a newly formed APAC Support team.…
About the role: Application Support Analyst (on site 5days) This role involves problem-solving to support trading applications and exchange connectivity for Global Derivatives Markets. Joining an award-winning…
About the role: Junior Application Support Analyst (on site) This role involves problem-solving to support trading applications and exchange connectivity for Global Derivatives Markets. Joining an award-winning…
Leads IC backend physical design tasks, including floorplanning, clock/power architecture, and tapeout, collaborating with front-end teams to ensure chip design integrity.
Bioinformatics Scientist designing qPCR/dPCR/CE assays and building computational pipelines for large-scale assay development at Thermo Fisher Scientific in Singapore.
R&D engineer responsible for physical design and implementation of high-performance System-On-Chip ASICs (500M–800M gates) at 5nm/3nm/2nm nodes using commercial and in-house EDA tools, collaborating with RTL teams and supporting customers.
This role involves architecting and designing high-speed mixed-signal SerDes circuits and high-performance digital circuits for automotive audio-video applications. The engineer will manage the full ASIC design flow from RTL to GDSII, including verification, synthesis, and timing closure.
Make your mark at Comcast -- a Fortune 30 global media and technology company. From the connectivity and platforms we provide, to the content and experiences we create, we reach hundreds of millions of customers,…
Altech Solutions is hiring a Systems Administrator to support NASA's Engineering Directorate at Langley Research Center in Hampton, Virginia. This role lives inside engineering and laboratory environments — the…
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and is responsible for powering Microsoft’s Intelligent Cloud mission.…
Administer and optimize large-scale MySQL (sharded/HA) and other database clusters (Postgres, MongoDB, Clickhouse) handling terabyte-to-petabyte datasets, with a focus on query tuning, capacity planning, and backup/recovery at a partnership marketing SaaS company.
C++ Software Developer/Engineer working on low latency trading platforms using C/C++ in an agile environment. Core technologies include C++, STL/Boost, Linux/Unix, and scripting languages like BASH, Perl, and Python.
Lead a team to design and integrate ASIC/SOC components, focusing on power and clock management, while collaborating with cross-functional hardware and software teams.
Senior/Principal Physical Design Engineer at Fractile, responsible for end-to-end ASIC/SoC physical design implementation (floorplanning, placement, CTS, routing, sign-off) using EDA tools like Cadence Innovus, Synopsys Fusion Compiler, and Mentor Graphics Calibre, optimizing PPA metrics and collaborating with cross-functional teams.
We couldn't check your fit for this role — add a CV to your profile to see it next time.