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Architect GPU performance by analyzing bottlenecks in high-end SoCs and GPUs, modeling hardware at multiple abstraction levels, and optimizing for graphics, ML, and automotive workloads.
Architect and implement firmware for reliability, availability, serviceability, and power management across NVIDIA’s networking platforms, collaborating with hardware, software, and validation teams.
Design and implement GPU micro-architecture in RTL using Verilog/VHDL, optimizing for power, performance, and area while collaborating with verification and physical design teams.
Develop embedded firmware for AMD’s networking products, collaborating with hardware teams to refine silicon designs and optimize network stacks for cloud and AI systems.
Designs and implements high-performance, low-power security engines and RISC-V processor modules in RTL using Verilog/System-Verilog for NVIDIA’s AI and cybersecurity products.
Develops the operating system and software stack that powers custom trading hardware, integrating low-level hardware with Python, C/C++, and embedded systems.
Develop and verify complex SoC FPGAs for high-data-rate networking or DSP applications using VHDL, Verilog, and Xilinx tools, while collaborating on hardware/software co-design.
Staff engineer verifying next-gen eFPGA and SoC designs using UVM, SystemVerilog, and end-to-end silicon verification flows.
Designs digital SoC/ASIC IP blocks and subsystems for automotive electronics, writing RTL in Verilog/VHDL and guiding physical implementation and verification flows.
Design verification engineer to validate custom silicon for AI hardware, writing test plans and debugging RTL in UVM/C++ for complex SoCs.
Design and verify non-volatile memory (NVM) circuits for analog AI compute-in-memory chips, including high-voltage blocks and interfaces with analog computation units.
Design and develop embedded electronics and firmware for precision scientific instruments, microscope systems, and research tools using C/C++, Altium, and ARM Cortex.
Senior SoC Design Engineer at NVIDIA to architect and deliver next-gen system-on-chip designs, collaborating across teams to ensure first-time-right RTL, synthesis, and validation using Verilog/SystemVerilog and AMBA protocols.
Principal FPGA Engineer designs and verifies firmware for radar and electronic warfare systems using VHDL/SystemVerilog, PCIe/Ethernet, and MATLAB, ensuring safety-critical performance in defence applications.
Designs FPGA firmware for defence electronics using VHDL/Verilog, working on sensors and secure communications while requiring UK security clearance.
Develop and maintain microscopy-control software for advanced light- and electron-microscopy platforms, integrating hardware and enabling automation and real-time data workflows.
Design and verify FPGA/ASIC digital circuits for aerospace/defense avionics, writing RTL in VHDL/Verilog and ensuring DO-254 compliance.
Verify GPU memory subsystem and interconnect IP designs using SystemVerilog/UVM, testplans, and coverage-driven flows to ensure correctness and performance.
Designs and verifies digital functions for WiFi MAC IP, subsystems, or ICs using Verilog, C/C++, and Python; debugs and validates chips for communications devices.
Design and maintain FPGA firmware for aerospace systems, including SoC integration, signal processing, and space-grade communication interfaces.
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