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Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to…
Building Name: UVMMC - In State Remote WorkerLocation Address: 111 Colchester Ave., Burlington VermontRegularDepartment: VTEHDI/DHHDB Educ Svc ProgShift: DaySalary Range: Min $30.47 Mid $38.09 Max $45.71Recruiter: Kate…
#WeAreIn to create tiny chips and big careers. Are you ready to take the first step of your career? Let's shape the future together! Whether you join as a student, intern or trainee, you'll be part of something…
Lead Data Engineer owning enua Pharma's Databricks data platform at a fast-growing medical cannabis producer in Cologne: designing the company-wide data model, integrating ERP/CRM and market data, building LLM-based internal tools, and setting engineering standards — hands-on with Python, SQL, and Databricks, supported by one junior engineer.
Lead a design verification team at Renesas in Bengaluru responsible for functional verification of complex digital IPs, subsystems, and SoCs, owning verification strategy, planning, and sign-off through first silicon. Core technologies include SystemVerilog, UVM, assertions, coverage-driven, formal verification, and emulation, plus people management of the verification org.
Unser Marketing Team bildet bei OMR die zentrale Anlaufstelle für alles, was von und mit OMR nach außen kommuniziert wird. Dadurch sind wir mit allen Abteilungen im engen Austausch und haben unsere Finger bei den…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The engineer will work with a global team to develop and maintain high-quality C/C++ software for…
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Sr Staff Engineer building and leading ASIC design verification at Synopsys: architecting UVM/SystemVerilog testbenches for interface IP (PCIe/CXL) that ships in real silicon, writing constrained-random tests and assertions, driving coverage closure, and mentoring verification engineers.
Обязанности: Разработка и верификация цифровых устройств на основе ПЛИС (FPGA) для спутниковых систем связи. Участие во всем жизненном цикле проекта: от анализа требований и разработки архитектуры до реализации,…
Lead verification of safety-critical FPGAs for Radiant's nuclear microreactor control, instrumentation, and communication systems — building SystemVerilog/UVM testbenches, driving coverage closure, and collaborating with RTL, hardware, and embedded software teams. Onsite in El Segundo, CA.
Renesas is hiring a Senior Principal Design Verification Engineer in Plano, TX to lead verification of its Automotive PMIC product line — architecting mixed-signal (RNM/AMS) verification environments, running RTL and gate-level simulations, debugging analog blocks like regulators, and mentoring junior engineers. Core tools include SystemVerilog, UVM, Spectre, and Xcelium.
Mit dem OMR Festival veranstalten wir das größte Festival für das Digital-Business in Europa mit zuletzt über 70.000 Besucher*innen in 2026. Hinter den Kulissen sorgt unser F&B Team für reibungslose Abläufe und das…
ALTEN is hiring an FPGA specialist in Bordeaux to design and validate complex FPGA/SOC designs for critical embedded aerospace systems (video, flight computers, energy management) at major aerospace clients. Day-to-day work spans RTL coding in VHDL/Verilog, testbench development, DO-254-compliant documentation, and technical collaboration with hardware/software teams.
OMR Reviews hat als jüngstes Mitglied des OMR Kosmos die Ambition, sich als führende Software-Bewertungsplattform im DACH Markt zu etablieren. Auf OMR Reviews bringen Erfahrungsberichte echter Nutzer*innen Transparenz…
AFRY is hiring an FPGA designer in Stockholm to work primarily with defense-industry clients on safety-critical products. Day to day: FPGA design (and possibly verification) plus involvement in system work, requirements, testing, and delivery. Core tech: VHDL, ideally also Verilog/SystemVerilog, and multi-clock-domain design.
Über enua enua ist ein ganzheitlicher Hersteller von medizinischem Cannabis mit der Mission, Patientinnen und Patienten einen sicheren und verlässlichen Zugang zu ermöglichen. Als zweitgrößter Anbieter im deutschen…
Staff-level VLSI design verification engineer at Sandisk in Bengaluru who leads verification of complex IP blocks and SoC designs: building UVM testbenches, driving functional coverage closure, writing SystemVerilog assertions, and running regressions with Cadence tools (Xcelium, Verdi, JasperGold), while mentoring junior engineers.
Senior silicon design engineer on AMD's Radeon Technologies Group in San Jose (hybrid), implementing and verifying DFT architecture: scan insertion, ATPG pattern generation and gate-level simulation, test coverage/cost analysis, and post-silicon bring-up support using tools like Tetramax, Testkompress, and VCS.
At AMD's San Jose office (hybrid), a Sr. Staff ASIC Design Engineer joins the front-end design/integration team for next-generation graphics and compute silicon, focusing on DFT: scan insertion, ATPG pattern generation, gate-level simulation verification, test-cost analysis, and post-silicon bring-up. Tooling includes VCS, TetraMAX/DFTMAX, TestKompress, Perl/Shell, and Verilog RTL.
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