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Build and debug FPGA-based emulation platforms (Synopsys HAPS) to validate complex SoC/ASIC designs and enable early software execution before silicon tape-out.
Design and implement FPGA blocks for high-rate data transport and signal processing in satellite ground stations, using Verilog/SystemVerilog and Python.
Designs and implements testability features for ASIC/SoC chips, including scan chains, MBIST, and ATPG flows, to ensure manufacturability and high fault coverage.
Design and implement FPGA-based networking and DSP blocks for satellite ground stations, ensuring resilient, high-rate data links for real-time space communications.
Verify and validate AMD’s next-gen GPU and SOC designs using Verilog/SystemVerilog, UVM, and emulation platforms like Veloce/Zebu to ensure functional correctness and performance.
Design and implement high-performance RISC-V CPU cores, focusing on microarchitecture, RTL coding, and collaboration with verification and physical implementation teams.
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
Design Verification Engineer at Cisco in Armenia builds and runs testbenches in SystemVerilog to validate ASIC designs, debug with DVE/Verdi, and script in Tcl/Python/Perl.
Design and verify high-performance network switch ASICs using SystemVerilog, UVM, and C++, developing complex verification environments and test plans.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.
Leads SoC-level verification for a semiconductor company’s edge AI processor (GPNPU), designing testbenches, verifying subsystems (NoC, PCIe/UCIe, DDR), and ensuring hardware-software co-simulation coverage using UVM, Verilog, assembly, and Python.
Design and verify security IP for SoCs, focusing on cryptography, key management, secure boot, and hardware root of trust using UVM, SystemVerilog, and C.
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
Design and run verification environments for next-gen eFPGA and SoC IP using UVM, SystemVerilog, and assertions to ensure silicon tape-out quality.
Lead the design, testing, and integration of FPGA firmware for high-performance imaging systems, collaborating with hardware and software teams to meet manufacturing requirements.
Join Kyocera International, Inc. We’re hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility! Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education,…
Design and verify non-volatile memory (NVM) circuits for analog AI inference chips, including high-voltage blocks and peripheral logic, using SPICE and Verilog-A.
Design and implement FPGA/ASIC applications using OCaml/Hardcaml, Verilog, and C, focusing on high-level tools for hardware development and testing.
Designs and verifies hardware components for Microsoft's cloud infrastructure, focusing on formal verification methods and AI-driven solutions to ensure chip reliability and performance.
Senior FPGA Engineer, Cyber Location: Washington, District of Columbia, United States Department: AFS : Discovery Engineering : Cyber Anduril Industries is a defense technology company with a mission to transform U.S.…
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