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Обязанности: Разработка и верификация цифровых устройств на основе ПЛИС (FPGA) для спутниковых систем связи. Участие во всем жизненном цикле проекта: от анализа требований и разработки архитектуры до реализации,…
Lead verification of safety-critical FPGAs for Radiant's nuclear microreactor control, instrumentation, and communication systems — building SystemVerilog/UVM testbenches, driving coverage closure, and collaborating with RTL, hardware, and embedded software teams. Onsite in El Segundo, CA.
Renesas is hiring a Senior Principal Design Verification Engineer in Plano, TX to lead verification of its Automotive PMIC product line — architecting mixed-signal (RNM/AMS) verification environments, running RTL and gate-level simulations, debugging analog blocks like regulators, and mentoring junior engineers. Core tools include SystemVerilog, UVM, Spectre, and Xcelium.
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ALTEN is hiring an FPGA specialist in Bordeaux to design and validate complex FPGA/SOC designs for critical embedded aerospace systems (video, flight computers, energy management) at major aerospace clients. Day-to-day work spans RTL coding in VHDL/Verilog, testbench development, DO-254-compliant documentation, and technical collaboration with hardware/software teams.
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AFRY is hiring an FPGA designer in Stockholm to work primarily with defense-industry clients on safety-critical products. Day to day: FPGA design (and possibly verification) plus involvement in system work, requirements, testing, and delivery. Core tech: VHDL, ideally also Verilog/SystemVerilog, and multi-clock-domain design.
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Staff-level VLSI design verification engineer at Sandisk in Bengaluru who leads verification of complex IP blocks and SoC designs: building UVM testbenches, driving functional coverage closure, writing SystemVerilog assertions, and running regressions with Cadence tools (Xcelium, Verdi, JasperGold), while mentoring junior engineers.
Senior silicon design engineer on AMD's Radeon Technologies Group in San Jose (hybrid), implementing and verifying DFT architecture: scan insertion, ATPG pattern generation and gate-level simulation, test coverage/cost analysis, and post-silicon bring-up support using tools like Tetramax, Testkompress, and VCS.
At AMD's San Jose office (hybrid), a Sr. Staff ASIC Design Engineer joins the front-end design/integration team for next-generation graphics and compute silicon, focusing on DFT: scan insertion, ATPG pattern generation, gate-level simulation verification, test-cost analysis, and post-silicon bring-up. Tooling includes VCS, TetraMAX/DFTMAX, TestKompress, Perl/Shell, and Verilog RTL.
Staff modeling architect at a silicon-photonics AI chip startup: builds performance/energy models and bit-accurate functional models of an optical AI inference accelerator, co-designing tiling, ISA, and memory hierarchy with compiler and RTL teams. Core stack: modern C++, Python (NumPy/Pandas), simulator kernels (SystemC/gem5-style), Verilator/SystemVerilog.
Meet the Team We are part of the Hardware Platform Group, with our team specializing in FPGA development. Our work spans both sophisticated data-path and challenging control-path FPGAs. The design process includes…
Senior Design Verification engineer at Lattice Semiconductor in Pune verifying complex FPGA/SOC silicon. Day to day: building reusable UVM testbenches, coverage-driven and directed testing, integrating VIPs, and low-power (UPF) and HW/FW verification through tape-out using SystemVerilog.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
Alternate Job Titles Digital Verification Senior Staff Engineer Mixed-Signal PHY Verification Lead ASIC Verification Sr Staff Engineer RTL/GLS Verification Senior Staff Engineer High-Speed Interface Verification Senior…
Alternate Job Titles Digital Design Senior Staff Engineer ASIC Design Sr Staff Engineer RTL Sr Staff Engineer Senior Staff Digital IP Designer We Are Synopsys is the leader in engineering solutions from silicon to…
## WIR SIND SMART Seit 2008 sind wir Entwicklungspartner für intelligente vernetzte Systeme. Unser Fokus liegt auf der Produktentwicklung, dem Produktmanagement und der technischen Beratung für unsere Kunden. Unser…
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