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About KATIM KATIM is a leader in the development of innovative secure communication products and solutions for governments and businesses. As part of the Secure Intelligence Systems cluster at EDGE, one of the worlds…
FPGA verification/test engineer at Navigator, a St. Petersburg maker of airborne navigation and avionics equipment (part of the defense industry). Day to day: building verification models for FPGA hardware, writing RTL module tests, testing DSP functional blocks, and running simulation and integration testing with Verilog, ModelSim, Xilinx Vivado, Linux, and Rational DOORS. Office-only role.
A senior ASIC design engineer who designs, verifies, brings up, and debugs digital subsystems in electro-optical SoCs for Ayar Labs' co-packaged optics that move data for AI systems. Day to day: RTL in Verilog/SystemVerilog, testbenches, timing constraints and documentation, and Python-driven silicon bring-up.
Senior physical design engineer who owns end-to-end implementation of complex mixed-signal SoC blocks — synthesis, place-and-route, static timing analysis, and physical verification — integrating digital, custom analog, and photonics components for Ayar Labs' co-packaged optics interconnects for AI. Core tooling includes Cadence/Synopsys flows (Genus, Innovus, ICC) plus DFT and scripting.
Owns and scales the front-end CAD/design automation flows for Ayar Labs' ASIC and SoC teams in Bengaluru: building Python/Tcl/Shell/Make tooling for lint, CDC/RDC, regressions, and signoff readiness, supporting Synopsys/Cadence/Siemens EDA deployments, and championing AI-assisted CAD agents and workflows.
Ayar Labs is hiring a hands-on ASIC engineer to design, verify, and bring up digital subsystems in electro-optical SoCs for its co-packaged optics products that move AI data over light. Day to day this means writing Verilog/SystemVerilog RTL, building testbenches, defining timing constraints, and debugging custom silicon with Python and firmware.
Sr. Staff Engineer designing and debugging digital subsystems for Ayar Labs' electro-optical ASICs (co-packaged optics that move AI data over light). Day to day: writing RTL in Verilog/SystemVerilog, building testbenches, defining timing constraints, and doing silicon bring-up/debug with Python, C/C++, and firmware — on-site in San Jose.
Sr. Staff Engineer in San Jose (on-site) building and validating system-level models of optical links for Ayar Labs' co-packaged optics (silicon photonics) I/O platform aimed at AI infrastructure. Day to day: link modeling studies, translating device variability into link budgets and yield, benchmarking models against measured data, using Python-based data analysis.
Ayar Labs is hiring a Principal ASIC Physical Design Engineer in Bangalore to own end-to-end physical implementation of mixed-signal SoCs that integrate digital, custom analog, and photonics blocks for its co-packaged optics engine. Day-to-day work covers synthesis, place-and-route, static timing analysis, DFT, and physical verification in leading-edge process nodes.
Senior ASIC Design Verification Engineer at Ayar Labs (Bengaluru, on-site) doing pre-silicon verification of complex SoCs with digital and mixed-signal blocks: building SystemVerilog/UVM testbenches, test plans and coverage closure for SerDes, parallel-link and on-chip interconnect IP within a small startup IC design team.
Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation…
Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring…
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and integration of digital systems in TetraMem’s AI accelerators. You’ll contribute to RTL design, simulations, and…
Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs Integrate and validate IP blocks within the larger system, ensuring seamless…
For over 20 years IC Enable has successfully provided design IP, IC products, services, and platform solutions to demanding customers ranging from startups to Fortune 50 members. Our design and product offerings focus…
IC Enable is seeking an experienced RTL Design Engineer to support digital IC development from architecture through implementation. This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design…
For more than 20 years, IC Enable has delivered world-class design IP, semiconductor products, engineering services, and platform solutions to customers ranging from innovative startups to Fortune 50 companies. Our…
LHP Engineering Solutions is a Functional Safety global leader committed to creating safe transportation with developing technologies such as Electric Vehicles, Advance Driver Assistance Systems. At LHP we ensure…
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