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DevOps Engineer at a quantum technology scaleup, building and maintaining CI/CD pipelines across FPGA, embedded, and software projects using Podman, Terraform, Ansible, and GCP. No quantum computing experience required.
Designs high-speed, mixed-signal, RF, and power PCBs for spaceborne radar hardware, ensuring signal integrity and compliance with aerospace standards using Altium Designer.
Designs and owns the architecture of a new UPS product from concept to manufacturing, defining hardware/software boundaries, topologies, and compliance strategies while leading cross-functional teams and customer-facing technical discussions.
Our Client is a global technical group specializing in electric power conversion, serving customers in 47 countries across OEM and Aftermarket & Service segments, with R&D, production and service sites in…
Tasks summary: Architecture Concept & Requirements • Translate mission‑level requirements into C&DH functional and non‑functional specifications. • Produce System Requirements, Interface Control (ICDs), and…
Leads a team specializing in hardware/firmware co-verification for AMD’s security IP subsystems, including cryptography, compression, and DMA accelerators, using UVM/SystemVerilog and FPGA prototypes. Focuses on verification architecture, performance optimization, and team management for next-gen SoCs.
Design and run C/C++ tests, firmware, and FPGA RTL for embedded SoC validation, debug silicon bring-up issues, and automate flows with Python.
Develops embedded firmware for power electronics control systems in EV charging hardware, using C/C++ and real-time OS tools to design and validate grid-tie inverters and DC/DC converters.
Designs and implements embedded firmware for EV charging hardware, focusing on power electronics control for fast chargers and related converters using C/C++ and real-time systems.
Intern designs FPGA/ASIC hardware for ultra-low latency trading systems, coding in SystemVerilog/Python and bringing designs to life on real silicon.
Build and optimize diagnostics software to validate AMD’s security hardware IP across CPUs, GPUs, and accelerators, using C/C++ and AI-driven tools to root-cause issues from pre-silicon to production.
Designs and optimizes low-level GPU kernels for AI inference, focusing on performance, correctness, and hardware efficiency while mentoring engineers and collaborating with ML teams.
Position Overview As a Lead Hardware Engineer in our Systems Engineering group, you will be responsible for delivering systems and sub-assemblies, taking them from concept to production. These hardware designs…
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
ON-SITE IN MONTREAL IS PREFERRED; REMOTE OR HYBRID IS POSSIBLE FOR THE RIGHT CANDIDATE. * OPEN TO US AND EUROPE BASED CANDIDATES * The selected candidate will contribute to the entire payload lifecycle — from…
Designs and validates high-performance digital boards and FPGA firmware for advanced electronic warfare and secure communications systems, from concept to production.
Graduate rotational program for Technical Sales Engineers to rotate through product marketing, technical marketing, business ops, and sales, focusing on Embedded x86/FPGA tech to consult with customers and drive solutions.
Develop and verify embedded firmware in C/C++ for mixed-signal power management ICs, collaborating with RTL teams to define hardware interfaces and ensure ROM-ready code.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
ASIC Design Verification Engineer responsible for owning verification strategy, coverage closure, and system-level testing for AMD’s mixed-signal power management IP, including RTL design and collaboration with analog/firmware teams.
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