Tech jobs

Open 25d North AmericaFull-timePrincipal H-1B sponsor history

Principal Engineer, PHY/MAC Design (P)

Asic FPGA IoT Prototyping Rtl +4 skills

Principal Engineer designing wireless PHY/MAC silicon at InnoPhase IoT in San Jose: builds end-to-end simulation frameworks, DSP engines, and SystemVerilog RTL for WiFi/cellular physical layers, then drives designs through synthesis, timing closure, and verification with cross-team collaboration.

216K – 220K $

Samsung Semiconductor

Open 137d North AmericaFull-timeStaff H-1B sponsor history

Senior Staff Engineer, Design Verification

AI Automation Candidate Experience C++ FPGA +6 skills

Designs and automates verification environments for AI accelerator IP blocks using UVM, SystemVerilog, and C/C++, ensuring functional and performance validation.

189K – 301K $

Advanced Micro Devices, Inc

Open 131d North AmericaStaff

Staff DFx Methodology Architect

AI Bash CAD Embedded Systems Firmware +6 skills

Architect and implement DFx (Design for Test, Debug, etc.) methodologies and RTL for AMD’s AI-focused SoCs and ASICs, ensuring power, performance, and timing targets while collaborating across global teams.

Advanced Micro Devices, Inc

Systems Design Engineer - Memory Enablement

Open 25d APAC

AI Asic Bash C++ Firmware +6 skills

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

Spyrosoft

AI Automation C++ Embedded Software Ethernet +10 skills

Senior FPGA Engineer (Defence & Security)

EuropeContractSenior

Poland

Tech Stack: VHDL, Verilog, SystemVerilog Xilinx Vivado, AMD Vitis, Intel Quartus SoC FPGA Platforms (Zynq, MPSoC, SoC FPGA) Embedded C/C++ Python / Scripting Languages UVM (Universal Verification Methodology) UART,…

Neurealm

RTL Design Engineer

APACFull-time

FPGA Prototyping Rtl Verilog VHDL

RTL Design Engineer Experience : 5 - 8 Years Location : Bangalore / Kochi / Chennai / Pune Job Type : Full-time About the Role : We are looking for a skilled RTL Design Engineer with hands-on experience in ASIC/SoC…

Neurealm

Senior RTL Design Engineer - ASIC/SoC

APACSenior

Asic Firmware FPGA Prototyping Rtl +2 skills

Senior RTL Design Engineer / Lead About the Role : We are seeking an experienced Senior RTL Design Engineer / Lead to drive RTL development and integration for complex ASIC/SoC projects. The role requires strong…

Neurealm

Principal/Lead RTL Design Engineer - ASIC/SoC

APACPrincipal

Automation Firmware FPGA Prototyping Root Cause Analysis +4 skills

Role : Principal / Lead RTL Design Engineer About the Role : We are looking for a highly experienced Principal / Lead RTL Design Engineer to provide technical leadership for complex ARM-based ASIC/SoC development…

BAE Systems, Inc.

North AmericaFull-timePrincipal

Principal FPGA Digital Design Engineer - Sign-on Bonus

Asic Bash C++ Ethernet FPGA +13 skills

Job Description BAE Systems, Countermeasure & Electromagnetic Attack Solutions (CEMA) has an open position for a Principal FPGA Digital Design Engineer! See what you’re missing. Our employees work on the world’s most…

scalian

Open 23d Europe Licensed UK sponsor

FPGA Engineer - Aerospace Sector

Spain

Como parte de nuestros proyectos, buscamos incorporar un/a Ingeniero/a de FPGA para participar en el desarrollo de soluciones FPGA embebidas , integradas en sistemas electrónicos y de computación complejos. La persona…

FPGA Verilog VHDL

careers.huaweirc.ch

Agentic AI AI Cloud LLM Machine Learning +5 skills

Research Intern – Hardware Optimization for AI Accelerators

EuropeInternshipIntern

Switzerland

Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships, we have established leading…

Renesas Electronics

Open 25d HybridAPACContractStaff

Senior Staff AMS Design Verification Engineer

Agile Asic Bash Cadence Virtuoso IoT +9 skills

Senior project lead of a team of engineers in the tasks of guaranteeing specification compliance of analog & mixed signal design by means of advanced verification methodologies and concepts. It involves definition,…

STR

Open 38d North AmericaFull-timeLead

Lead Software Developer

Analytics C++ Design Patterns Embedded Software Embedded Systems +11 skills

About the Team STR Sensors Division is at the forefront of developing advanced signal processing algorithms and prototyping systems for next-generation radar and electronic warfare technologies. The group fosters a…

STR

Open 27d North AmericaFull-timeSenior

Senior FPGA Reverse Engineer

Analytics C++ Embedded Systems FPGA MATLAB +9 skills

Senior engineer in STR's Cyber Division performing FPGA reverse engineering: analyzing gate-level netlists, using RTL simulation to understand designs, and building software tools to automate hardware RE, while briefing customers on findings. Requires strong FPGA/HDL experience and eligibility for a Top Secret clearance.

138K – 189K $

Emerald Technologies

Open 25d RemoteNorth AmericaPrincipal

Principal Hardware Design Engineer

Altium Embedded Systems Ethernet Firmware FPGA +7 skills

Design the Future. Solve Complex Challenges. Build Technology That Matters. Are you an accomplished hardware engineer who thrives on solving complex technical challenges and bringing innovative products from concept to…

SpaceX

Open 26d North AmericaFull-timeSenior

Sr. ASIC Design Engineer (Silicon Engineering)

Firmware Itar Python Rtl Verilog

Senior RTL/ASIC design engineer at SpaceX in Austin, TX developing next-generation ASICs for the Starlink satellite broadband system. Day to day: define micro-architecture, implement and integrate Verilog/SystemVerilog RTL, drive synthesis/timing closure with the implementation team, and support silicon bring-up and validation.

SpaceX

Open 26d North AmericaFull-timeSenior

Sr. ASIC Design Engineer (Silicon Engineering)

Firmware Itar Python Rtl Verilog

Senior RTL design engineer on SpaceX's Silicon Engineering team in Irvine, CA, developing next-generation ASICs for the Starlink satellite and ground network. Day to day: defining micro-architecture, implementing Verilog/SystemVerilog RTL, supporting synthesis/timing closure, and participating in silicon bring-up and validation.

165K – 265K $

Advanced Micro Devices, Inc

AI Analytics API Asic Automation +18 skills

AI Platform Engineer, Silicon Design Infrastructure

Open 26d North America

An engineer who builds and runs the development infrastructure and AI services behind AMD's AI-assisted silicon design program — modernizing source control, CI/CD, and compute/storage platforms, plus telemetry and benchmarking to measure AI impact. Core stack spans Python, Git/GitHub, CI/CD, LLM ops, and EDA compute (LSF/Slurm, Linux) alongside ASIC design workflows.

NVIDIA Hungary Kft.