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Sr Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities:…
Intern designs FPGA/ASIC solutions for ultra-low-latency trading systems, writing and verifying RTL in SystemVerilog and bringing designs up on live hardware.
Design and verify custom silicon chips for next-generation data storage hardware, using RTL, Verilog/SystemVerilog, and digital logic while collaborating with cross-functional engineering teams.
Design and verify custom silicon and hardware for next-generation data storage devices, collaborating across ASIC, firmware, and systems engineering teams using RTL, Verilog, and embedded C/C++.
Build and maintain UVM/SystemVerilog testbenches to verify PCIe and memory-subsystem RTL, collaborating with architects and post-silicon teams to ensure robust, high-performance designs.
Camera Electronics Engineer Location: Bangalore, India; Bangalore, India Department: KaleidEO Experience: 2-5 years Work with the brightest minds, including ex-ISRO scientists and global space industry experts, at one…
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Verify next-gen power-management ICs for Apple’s PMU team, writing test plans and environments in SystemVerilog/Verilog-AMS to ensure high-quality silicon tape-outs.
FPGA Design Engineer Level 2 Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: No CLEARANCE…
An intern in AMD’s Singapore design center works on cutting-edge IC design tasks like analog/digital design, verification, or post-silicon validation using EDA tools such as Cadence and Synopsys, contributing to high-speed SerDes and AI-related chips.
Experienced FPGA Developer Location: Rancho Santa Margarita, CA, us Company Description CS Group USA, a subsidiary of CS Group, is a key player in the development and certification of safety-critical systems in the…
Analog/Mixed-Signal Design Engineer (f/m/d) Department: Product Team Location: Aachen, Germany Employment Type: FullTime About us We see the semiconductor industry as a realm of possibility. We see opportunity. We see…
Hardware Engineer – Host Processor Systems Location: Beaverton, OR, United States Department: Engineering Work Location: onsite Staff Hardware Engineer – Host Processor Systems Tektronix , an operating company of…
Design verification engineer at Apple’s Nabern office, verifying next-gen power-management ICs using mixed-signal verification flows, hardware description languages, and analog behavioral models to ensure high-quality silicon tape-outs.
Principal Engineer leading pre-silicon verification of complex digital SoCs, AI/ML accelerators, and high-speed peripherals using UVM, formal methods, and emulation for edge computing products.
Senior FPGA engineer designing high-performance radar, comms, and sensing systems using AMD Xilinx Zynq SoC devices and Vivado toolchain.
Designs low-power wireless System-on-Chip solutions, writing RTL code and guiding the SoC through synthesis, timing analysis, and tape-out while collaborating with global teams.
Lead hardware board design and system engineering for Cisco’s Edge and Access routing products, shepherding designs from concept through production and validation.
Lead physical design and implementation for complex semiconductor subsystems, driving RTL-to-GDSII flows, floorplanning, place-and-route, and timing closure for high-performance SoCs.
Designs and validates chip-level test structures (JTAG, MBIST, scan/ATPG) to ensure silicon quality and manufacturability, collaborating with design and verification teams.
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