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Designs and develops FPGA-based digital solutions for aerospace/defense systems, including RTL architecture, verification, timing closure, and system integration. Works in Agile teams, mentors junior engineers, and collaborates on mission-critical hardware projects requiring security clearance.
Staff Interface IP Verification Engineer (Pre-Silicon) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver…
Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered…
Principal Engineer- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible…
JOB SUMMARY WE WANT YOU! Du arbeitest gerne mit Daten und lebst eine Zero-Waste Policy? Du hast ein Händchen fürs Verhandeln und weißt genau, welche Produkte, wann benötigt werden und welcher Lieferant die beste…
Lead or Senior ASIC/FPGA Design Verification Engineer owning verification scope, building UVM and SystemVerilog environments, and driving verification closure across Boeing's aerospace and defense programs.
SyoSil is hiring ASIC/FPGA design and verification engineers to work on RF radio ASIC projects using SystemVerilog and UVM. The role involves full-cycle IP block development, from architecture to verification, within a collaborative, SCRUM-based international team.
Own verification planning and execution for a scalable cache-coherent interconnect subsystem using SystemVerilog and UVM in high-performance RISC-V SoCs.
RTL design and integration engineer on AMD's FPGA product team, driving silicon implementation using Verilog/SystemVerilog, EDA tools, and scripting automation.
Willkommen bei Österreichs führendem Anbieter technischer Dienstleistungen! Mit dem gebündelten Know-how von rund 500 IT-ExpertInnen und Engineering-SpezialistInnen entwickeln wir seit über 50 Jahren Lösungen für…
The Research Engineer will develop reinforcement learning environments and evaluations to improve AI models' capabilities in silicon design, including RTL generation and physical design optimization. The role requires deep expertise in chip design flows and EDA tools to bridge the gap between hardware engineering and large-scale AI training.
Wir suchen ab sofort Verstärkung für unser Team! Als Key Account Manager (m/w/d) bist du das Gesicht unseres Unternehmens bei unseren wichtigsten Kunden und treibst den strategischen Ausbau dieser Partnerschaften…
Mitwirken bei der Konzeption und Umsetzung von Produkt- und Vertriebskampagnen in verschiedenen Medienkanälen Unterstützung bei der Umsetzung von zielgruppenspezifischen Werbeaktivitäten für kommunale Dienste,…
Senior IP Design Verification Engineer responsible for pre-silicon verification of Silicon IPs for Bosch's Automotive Chiplet Systems using UVM/SystemVerilog, UCIe, and AXI protocols.
Gestalte die Zukunft unserer Finanzbuchhaltung aktiv mit: In dieser verantwortungsvollen Position übernimmst Du eine Schlüsselrolle im Treasury- und Finanzierungsmanagement, treibst die Digitalisierung von…
Overview Microsoft is the world’s center of expertise on topological quantum computing. We are building a scaled, fault‑tolerant quantum computer grounded in topological qubits and integrated end‑to‑end with the Azure…
The application window is expected to close on: 09/10/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Job Description This role requires being…
New College Graduate Hardware ASIC Engineer role at NVIDIA in Shanghai, focused on SoC/chip design, verification, DFT, and post-silicon validation using VLSI, RTL, UVM, and physical design methodologies.
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