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Design and implement high-performance FPGA logic for next-gen NAND Flash storage systems using Xilinx tools and RTL, while collaborating on embedded firmware and system validation.
Designs, validates, and deploys large-scale GPU clusters for an AI-infra startup, negotiating with CSPs and vendors to ensure optimal power, cooling, and high-speed networking for AI workloads.
Design and validate next-gen accelerator boards for AI/ML/HPC using Openchip silicon, spanning schematic reviews, PCB layout, bring-up, validation, and system integration.
Designs and verifies RTL IP blocks for networking solutions, collaborating with architects and physical design teams to ensure first-pass silicon success.
Build and debug FPGA-based emulation platforms (Synopsys HAPS) to validate complex SoC/ASIC designs and enable early software execution before silicon tape-out.
Intern in firmware engineering designing, testing, and maintaining C++/Python code for storage devices with SAS/SATA/PCIe interfaces and embedded systems.
Develops and maintains firmware for hard drives using C++, Python, and embedded systems, ensuring compatibility with SAS, SATA, and PCIe interfaces.
Design and develop high-performance NAS and enterprise storage hardware, including PCB schematics, power delivery, and system validation with PCIe, NVMe, and Ethernet interfaces.
Designs and validates high-speed Ethernet hardware for enterprise switches, including schematics, PCB layout, signal integrity, and system bring-up.
Verify and validate AMD’s next-gen GPU and SOC designs using Verilog/SystemVerilog, UVM, and emulation platforms like Veloce/Zebu to ensure functional correctness and performance.
Lead validation and testing of enterprise PCIe/NVMe SSDs, design test plans, debug failures with firmware and hardware teams, and automate tests using Python/C/C++.
Architect high-speed interconnect subsystems (PCIe, CXL, UA Link) for next-gen SoCs, defining coherent/non-coherent communication architectures across mobile, automotive, datacenter, and IoT markets.
Build low-level embedded software and drivers for next-gen networking platforms, programming NPUs/ASICs and enabling high-performance routing systems in Linux environments.
Design and verify high-performance network switch ASICs using SystemVerilog, UVM, and C++, developing complex verification environments and test plans.
Leads SoC-level verification for a semiconductor company’s edge AI processor (GPNPU), designing testbenches, verifying subsystems (NoC, PCIe/UCIe, DDR), and ensuring hardware-software co-simulation coverage using UVM, Verilog, assembly, and Python.
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
Lead the design, testing, and integration of FPGA firmware for high-performance imaging systems, collaborating with hardware and software teams to meet manufacturing requirements.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Summary We are looking for an experienced Principal Analog Design Engineer to drive the design and…
Lead Software Engineer specializing in Verification IP (VIP) development for electronic design software, focusing on layered protocols like UCIe, PCIe, CXL, and Ethernet using SV/UVM, with hands-on C/C++ scripting and cross-functional collaboration.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
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