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SMMU Senior Lead Design Verification Engineer Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group…
RTL Design - Sr Lead Engineer Location: Noida, Uttar Pradesh, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
DSP / NPU Staff Design Verification Engineer Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
LPASS Design Verification Sr Lead Engineer Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
We're hiring an HPC SoC Timing Design Engineer/Leader for a global semiconductor company developing flagship automotive SoCs — large-scale chips integrating CPU, cache, memory, high-speed interfaces, AI, video,…
Lead the design of a next-generation edge SoC for a stealth startup, defining microarchitecture, driving PPA tradeoffs, and integrating high-performance IP to power a custom computing platform.
Designs high-speed electronic systems and PCBs for clients in aerospace, telecom, and other advanced industries, using tools like OrCAD and Cadence Allegro.
Design verification engineer leading pre-silicon verification for complex SoCs, using UVM, SystemVerilog, and formal methods to ensure correctness of AI/ML accelerators, processors, and interconnects.
Designs and integrates ARM-based microcontroller subsystems for automotive applications, collaborating with cross-functional teams to deliver robust SoC solutions for modern vehicles.
Designs and verifies ASIC/FPGA chips for high-speed optical transmission systems, using VHDL/Verilog and industry tools to optimize performance and power in coherent networking hardware.
Designs and verifies ASICs and FPGAs for high-speed optical transmission systems, implementing signal processing algorithms and collaborating with global teams to optimize power and performance.
Designs and implements secure, high-performance IP blocks for Intel’s Unified Chassis, focusing on AXI/APB bridges, ECC/parity schemes, and RAS/debug telemetry for SoC reliability.
Integrate hardware security IP (RoT, crypto engines, HSMs) into AI-focused SoCs, define secure boot/attestation, and architect protections against physical/side-channel attacks for data-center hardware.
Verifies CPU logic before manufacturing by writing test benches in SystemVerilog/UVM, running simulations, debugging failures, and collaborating with architects to meet specs.
Working student role in DRAM design, assisting engineers with IC schematics, simulations, and verification for high-performance memory solutions in Munich.
Design and verify ASICs for HP printers, leading RTL coding, verification, and silicon validation while collaborating with cross-functional teams to deliver embedded solutions.
Design FPGA/ASIC digital systems for radar, electronic warfare, and communications using Verilog/VHDL, high-speed interfaces, and PCB tools while leading teams and collaborating across engineering and business functions.
Lead the physical design and implementation of high-performance processor chips from RTL to GDS in advanced nodes (5nm–2nm), managing global teams and sign-offs for timing, power, and DFM.
Lead the physical design and methodology for next-gen high-performance processor chips, managing RTL-to-GDS flows, timing, power, and sign-offs in advanced nodes (5nm–2nm) for server, 5G/6G, and networking applications.
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