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Design and execute firmware verification plans for SSD products, using Python and storage protocols like NVMe to ensure reliability and performance in enterprise and automotive markets.
Lead the design and integration of high-speed digital hardware, FPGA/SoC architectures, and signal processing for defence/aerospace systems, ensuring compliance with strict standards.
Principal Firmware Engineer in Luton designing and auto-generating firmware for complex digital systems using MATLAB, Simulink, Verilog, and FPGA tools.
Develop and debug low-level C firmware for NVIDIA network adapters, acting as the first-line technical support for Chinese customers and implementing requested features.
Design and verify ASIC blocks and full chips for Cisco’s networking hardware using SystemVerilog/UVM, then bring up silicon and analyze performance.
Principal engineer designing and verifying PCIe/CXL IP subsystems in SystemVerilog for Marvell’s custom SoCs powering hyperscale cloud and AI data centers.
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Design high-performance board-level systems for storage and networking hardware, focusing on high-speed SerDes, signal/power integrity, and production-ready PCB layouts.
Lead FPGA architecture and RTL development for real-time medical systems, guiding Verilog/SystemVerilog implementations, timing closure, and hardware bring-up in a regulated healthcare environment.
Principal Design Engineer at Microchip Technology leading hardware/firmware co-development and pre/post-silicon verification using emulators and FPGA platforms for SoC devices.
Principal Linux Kernel Engineer at NVIDIA to lead upstream Linux kernel development for CPU Server platforms, shaping hardware architecture and collaborating with the open-source community.
Lead firmware engineering for datacenter servers, designing and prototyping BIOS/UEFI and BMC firmware while ensuring security and deployability for Oracle Cloud Infrastructure.
Designs and develops the Autonomous Driving Kit (AD-Kit) system, including embedded computes, sensors, and data buses, while ensuring functional safety and cybersecurity compliance for autonomous trucking technology.
Design and build low-level network systems software in C/C++/Python to control hardware components like FPGAs, NICs, and sensors on Arista switches and routers.
Design and manufacture multilayer RF, mixed-signal, and high-speed PCBs for space-economy connectivity using Altium Designer and RF layout techniques.
Leads RTL design for Google’s custom silicon solutions, focusing on ASIC development for SoC/VLSI, Verilog/SystemVerilog coding, and hardware-software integration to power Google Cloud and consumer products like Vertex AI.
Build and maintain the high-reliability Linux OS powering xAI’s supercomputer network, writing device drivers and optimizing hardware performance for AI workloads.
Architect and debug AMD’s CPU/GPU solutions for datacenter partners, running proofs-of-concept, root-cause analysis, and competitive TCO studies to accelerate new platform deployments.
Lead a team developing UEFI-based firmware (BIOS) for industrial automation hardware, debugging across the stack, and ensuring compliance with customer coding standards.
Define and market next-gen SSDs for hyperscale data centers, working with cloud and AI customers to align product roadmaps with their infrastructure needs and drive design wins.
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