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Builds and tests Jasper, a formal-verification tool for clock-domain-crossing issues in chip design, using C++ and Unix workflows.
Lead a team enhancing Jasper, a formal verification tool for clock domain crossing in hardware design, using C++ and Unix in a fast-paced R&D environment.
Design and verify ASIC/SoC hardware in Verilog/SystemVerilog, then evaluate and improve how AI models understand chip engineering tasks.
Designs and implements FPGA-based solutions for semiconductor test instruments, focusing on high-speed interfaces, memory subsystems, and signal processing using AMD/Xilinx or Intel/Altera tools.
Principal Analog Hardware Engineer designs and validates high-performance analog and mixed-signal circuits for next-generation test and measurement products in Santa Rosa, CA.
Designs and integrates PCIe, CXL, and other I/O subsystems for ARM-based SoCs, writing RTL, debugging, and collaborating with verification and backend teams.
Design and verify FPGA modules for advanced systems, collaborating with hardware and software teams using VHDL/Verilog and Xilinx tools.
Principal FPGA engineer designing and verifying VHDL/Verilog modules for high-reliability electro-optical systems, using Xilinx tools and OSVVM/UVM testbenches.
Designs and implements FPGA-based digital logic for space systems like satellite command and control, using VHDL/Verilog and AMD/Microchip tools.
Staff Hardware Engineer Tektronix , an operating company of Ralliant , is a place where people are challenged to explore the boundaries of what’s possible—bringing the digital future one step closer every day. Our work…
Design and prototype next-gen AI hardware using FPGAs, focusing on SoC emulation, high-speed interfaces like PCIe/LPDDR, and bring-up for analog compute-in-memory chips.
Design and implement real-time control systems for quantum networking hardware using FPGAs (Xilinx Zynq/Ultrascale) and embedded C/Rust, collaborating with physicists and engineers.
FPGA Lead/Architect/Implementor Location: Denmark - Kongens Lyngby Time Type: Full time Job Description Be visionary Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that…
CPU Core Logic Designer Location: US, California, Folsom Time Type: Full time Job Description Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU…
Design verification engineer at AMD building and maintaining test suites for next-gen CPU/DSP SoCs using SystemVerilog/UVM and scripting, ensuring functional and performance coverage.
Mixed Signal Logic Design Engineer Location: India, Bangalore Time Type: Full time Job Description Job Details: Job Description: The Memory PHY Group (MPG) within the Central Engineering Group (CEG) is looking for an…
Mixed-Signal Design Verification Engineer | Custom Location: Dallas, TX, United States We are seeking a talented Mixed-Signal Design Verification Engineer with experience in verifying high-speed wireline communications…
Designs and develops cryogenic CMOS analog circuits for quantum computing control systems, collaborating with hardware and physics teams to build scalable quantum platforms.
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