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Leads verification strategy for complex IC designs, guiding teams to build test environments, debug RTL, and improve coverage using UVM, SystemVerilog, and RISC-V protocols.
We are looking for a Chip Design DFT/Post Silicon Manager to develop the next generation DFT technologies. As a Chip Design DFT/Post Silicon Manager in the DFT team at NVIDIA, you will lead team that transfer our DFT…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities: • Engage with customers to understand verification challenges and identify suitable…
Design and verify next-gen FPGA devices using UVM, SystemVerilog, and AI/ML-enabled methodologies; collaborate with emulation and SoC teams.
Design and implement high-performance FPGA logic for embedded machine-vision systems, including RTL coding, simulation, and vendor selection, while collaborating with hardware and software teams.
Designs and verifies high-performance FPGA subsystems for network test and measurement hardware using Verilog/SystemVerilog and industry-standard EDA tools.
Verify CPU and SoC designs using SystemVerilog/UVM to catch bugs before silicon tape-out, collaborating with architects and RTL teams.
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Senior engineer building and improving ASIC verification infrastructure, CI/CD flows, and AI-assisted debug tools for GPU development at NVIDIA.
Designs and verifies digital semiconductor IP using Verilog/System Verilog, UVM, and Python/C++; performs CDC, DFT, and static timing checks; collaborates on verification test plans.
We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, from AI infrastructure and cloud computing to autonomous systems and…
Lead verification of DDR5/LPDDR5 memory interfaces for AMD server chips using SystemVerilog, UVM, and C/C++; mentor engineers and align firmware/software with hardware requirements.
Design Verification Engineer at AMD builds and runs SystemVerilog/UVM testbenches to validate DDR5, LPDDR5, and DFI memory interfaces for server products, collaborating with hardware, firmware, and software teams.
Develop and execute verification strategies for complex SoC components and systems, building SystemVerilog and UVM environments, verifying hardware-software interactions, analyzing performance and real-time behavior,…
Memwize is a VC-backed, stealth-mode startup building rack-level AI inference systems . We are seeking an experienced Design Verification Engineer to drive verification of complex next-generation AI/compute platforms.…
Design Verification Engineer at Cerebras building and validating the world's largest AI chip, ensuring first-silicon success through SystemVerilog/UVM testbenches and cross-functional collaboration.
Design and verify custom TPU silicon for Google’s AI workloads using SystemVerilog/UVM, driving full verification cycles from planning to tape-out.
With around 9,000 employees, AGRANA is the global leader in fruit preparations and also a major producer of fruit juice concentrates in Europe as well as being a key manufacturer of customised starch products and…
Building Name: UVMMC - 1 South Prospect StreetLocation Address: 1 South Prospect, Burlington VermontRegularDepartment: Addiction MedicineFull TimeStandard Hours: 40Biweekly Scheduled Hours: 80Shift: Day-8HrPrimary…
Design and lead digital architectures for power-management ICs in automotive and industrial systems using Verilog/SystemVerilog, synthesis, and verification flows.
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