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Design and verify mixed-signal ICs for current sensing, using RTL, SystemVerilog, VHDL, and UVM to ensure first-pass silicon success.
Designs and verifies mixed-signal ICs, leading pre-tapeout simulations and regressions to ensure silicon meets specs and is manufacturable.
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Zur Unterstützung unserer Web Agentur suchen wir zur Festanstellung (80 - 100%) Fachinformatiker_innen Systemintegration / Administration für Linux / DevOps (m/w/d) oder Personen mit einer ähnlichen Ausbildung.…
Design verification engineer building and debugging custom silicon for AI hardware using SystemVerilog, UVM, and formal tools.
Seit 1948 ist die DENK PHARMA als Familienunternehmen in mehr als 80 Ländern tätig. Unter unserem Slogan "Quality for your Health – Made in Germany" schaffen wir für alle Kunden mit unseren Produkten Zugang zur…
Role Overview We are looking for a Director of Silicon Validation to own the complete verification and validation lifecycle of our AI inference silicon, from pre-silicon functional verification, through hardware…
Continue to make an impact with a company that is pushing the boundaries of what is possible. At NTT DATA, we are renowned for our technical excellence, leading innovations, and making a difference for our clients and…
Make an impact with NTT DATA Join a company that is pushing the boundaries of what is possible. We are renowned for our technical excellence and leading innovations, and for making a difference to our clients and…
Design Verification Engineer at Cisco in Armenia builds and runs testbenches in SystemVerilog to validate ASIC designs, debug with DVE/Verdi, and script in Tcl/Python/Perl.
Design and verify high-performance network switch ASICs using SystemVerilog, UVM, and C++, developing complex verification environments and test plans.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.
Leads SoC-level verification for a semiconductor company’s edge AI processor (GPNPU), designing testbenches, verifying subsystems (NoC, PCIe/UCIe, DDR), and ensuring hardware-software co-simulation coverage using UVM, Verilog, assembly, and Python.
Design and run verification environments for next-gen eFPGA and SoC IP using UVM, SystemVerilog, and assertions to ensure silicon tape-out quality.
Lead Software Engineer specializing in Verification IP (VIP) development for electronic design software, focusing on layered protocols like UCIe, PCIe, CXL, and Ethernet using SV/UVM, with hands-on C/C++ scripting and cross-functional collaboration.
** Qualified candidates must be listed on the NM SHPO Directory at the Supervisory Archaeologist/Crew Chief level** FLSA Status: Non-Exempt, Hourly Reports To: Project Manager II Job Type: On-Call, Variable-Time…
Join Kyocera International, Inc. We’re hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility! Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education,…
Designs and verifies hardware components for Microsoft's cloud infrastructure, focusing on formal verification methods and AI-driven solutions to ensure chip reliability and performance.
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