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Principal Engineer leads verification strategy for next-gen UA Link Switch SoCs, using UVM/SystemVerilog to ensure first-silicon success for high-speed interconnect and memory subsystems.
About the team Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong…
Verify mixed-signal IPs (e.g., PCIe, USB4/Type-C PHYs) using SystemVerilog/UVM, EDA tools, and scripting to ensure performance and reliability before silicon tape-out.
Designs and verifies digital sub-circuits for high-performance micro-controllers using Verilog/SystemVerilog, synthesis, and formal verification, collaborating with analog and software teams.
Build and optimize simulation infrastructure for NVIDIA’s next-gen networking silicon, accelerating full-chip verification with SystemVerilog/UVM, Python, C/C++, and AI tools.
The application window is expected to close on: 10/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team The Common Hardware Group…
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
Lead verification of Cisco’s cutting-edge data-center ASICs, building DV environments, writing test plans, and ensuring full coverage with Verilog/SystemVerilog/UVM while collaborating with designers and software teams.
Staff Design Verification Engineer to verify high-performance CPU cores (frontend, midcore, load-store, prefetch) using SystemVerilog/UVM, debug microarchitectural issues, and drive coverage closure for next-gen RISC-V processors.
Own verification of high-performance CPU cores using SystemVerilog/UVM, writing test plans, assertions, and coverage to catch corner-case bugs in out-of-order pipelines.
Staff engineer verifying CPU cache and memory-subsystem designs using SystemVerilog/UVM, focusing on cache coherency, ordering, and corner-case bugs.
Design Verification Engineer builds and runs test environments for complex ASIC and mixed-signal IP using SystemVerilog/UVM, coverage analysis, and debug to ensure correctness before tape-out.
Designs and verifies mixed-signal SoCs for wireless systems, building analog/system models and testbenches in SystemVerilog/VerilogAMS to validate functionality before tape-out.
Design and implement high-performance CPU frontend features for RISC-V cores using Chisel/Verilog, focusing on instruction fetch, decode, and branch prediction while collaborating with verification and physical design teams.
Company: Qualcomm Israel Ltd. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm’s Peripheral IP organization is looking for a Senior Design Verification Engineer to develop…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible…
Building Name: UVMMC - Dental & Oral HealthLocation Address: 1060 Hinesburg Road, South Burlington VermontRegularDepartment: Dental ClinicPart TimeStandard Hours: 24Biweekly Scheduled Hours:Shift: DayPrimary Shift:…
Leads hardware verification for AI-generated chip designs, ensuring rigorous validation of custom ASICs at tapeout stage using SystemVerilog, UVM, and Python, while collaborating with AI/ML and architecture teams to refine verification strategies and methodologies.
**DARUM WIRST DU DICH BEI UNS WOHLFÜHLEN ** - Schlüsselrolle: In deiner Funktion trägst du aktiv dazu bei, dass Potsdam so lebenswert bleibt, wie es ist. - Arbeitsplatzsicherheit: Eine unbefristete Festanstellung in…
Lead AMD’s pre-silicon verification strategy, defining next-gen architectures and methodologies to ensure first-pass silicon success for complex SoC designs using advanced EDA tools and ML/AI innovations.
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