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Principal Hardware Engineer at HPE designs and validates high-end routing platforms, leading cross-functional teams in hardware development from concept to mass production.
Engineer validates high-bandwidth memory (HBM) components and testing flows, debugging failures and working with global teams to ensure product reliability and meet specifications.
Develops formal verification IP for hardware design using Verilog and SystemVerilog Assertions, focusing on industry-standard bus protocols like AXI or PCIe.
Principal Engineer designs advanced connectivity chips (Ethernet, USB, PCIe) using Verilog/SystemVerilog and ASIC flows, leading projects for Microchip’s Networking and Communications Group in Hauppauge, NY.
Designs and optimizes low-power, mixed-signal microcontroller chips from floorplan to GDSII tapeout using EDA tools like Innovus and Calibre.
Part-time intern supports a semiconductor digital design team by applying generative AI tools to automate workflows, analyze data, and create reports alongside studies.
Designs and leads the development of specialized test systems for space-grade electronics, including power, digital, RF, and mixed-signal systems, ensuring performance in extreme environments for satellite and space missions.
Designs and implements digital ASICs for scientific instruments, focusing on low-power, radiation-aware systems for particle detectors and high-energy physics applications using SystemVerilog/Verilog and EDA tools.
Designs and optimizes custom silicon hardware components for Google's products, focusing on performance, power efficiency, and integration using RTL and Verilog.
Designs and implements PCI Express IP blocks in Verilog/SystemVerilog for AMD’s server, client, GPU, and semi-custom chips, collaborating across RTL, verification, and post-silicon bring-up.
Designs and implements complex ASIC/SoC components for Google Cloud using RTL languages, collaborating with cross-functional teams to optimize performance, power, and area.
Designs and implements digital logic and IP for AI chips or SoCs using Verilog/SystemVerilog, verifies functionality, and integrates IP into larger systems with front-end design flows.
Designs and leads ASIC subsystems for Edge AI hardware, integrating high-performance interfaces and collaborating with software teams to optimize Google's direct-to-consumer products.
Designs and leads ASIC subsystems for edge AI hardware, integrating high-performance interfaces and collaborating with software teams to optimize latency and reliability in Google Cloud products.
Шукаємо кандидатів на позицію Embedded Engineer в українській інженерній компанії, що спеціалізується на розробці та виробництві засобів радіоелектронної боротьби (РЕБ). Це роль інженера повного циклу: робота і з…
Responsibilities In this role, the Digital Design SME will act as a Technical Advisor/Consultant to critical SI/SETA activities and serve as a primary interface between the Program customers/stakeholders, the technical…
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
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Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re…
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