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Principal Engineer leading pre-silicon verification of complex digital SoCs, AI/ML accelerators, and high-speed peripherals using UVM, formal methods, and emulation for edge computing products.
Designs low-power wireless System-on-Chip solutions, writing RTL code and guiding the SoC through synthesis, timing analysis, and tape-out while collaborating with global teams.
Lead FPGA design and architecture for defense electronics using VHDL, targeting Xilinx/Altera/Microsemi devices, and verify with constrained-random testing.
Building Name: Porter - Porter Medical Center Location Address: 115 Porter Drive, Middlebury Vermont Regular Department: Porter - Plant Operations Full Time Standard Hours: 40 Biweekly Scheduled Hours: Shift: Day…
Designs and integrates RTL blocks into SoCs, runs linting, CDC/RDC checks, synthesis, and gate-level simulations using tools like NCSim and VCS.
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Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and SoC solutions for edge connectivity applications.
Lead a team building and verifying hardware IP and SoCs for high-speed interfaces like PCIe and Ethernet using C/C++ and UVM, driving Cadence’s electronic design automation tools.
Principal Engineer in Marvell’s Design Verification team, building and running testbenches to verify high-speed storage IP like read channels and cryptographic engines using SystemVerilog/UVM and EDA tools.
Architects and implements pre-silicon verification strategies using UVM or formal methods, builds testbenches, and integrates block-level tests into chip-level environments for Intel hardware designs.
Validates mixed-signal hardware designs before fabrication, using SystemVerilog and UVM to ensure performance, power, and area goals are met.
Building Name: Porter - Porter Medical CenterLocation Address: 115 Porter Drive, Middlebury VermontRegularDepartment: Porter - Laundry & Environmental ServicesSalary Range: Min $20.50 Mid $25.48 Max…
Design Verification Engineer at AMD responsible for developing and maintaining tests to verify complex processor architectures and ASIC/SOC designs using Verilog, SystemVerilog, and UVM.
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Our team is looking for Design Verification engineers with hands-on experience in multiple projects with verification using UVM based methodology. Candidates must be able to work and integrate third party verification…
Designs and codes FPGA logic in VHDL for radar and electronic-warfare systems, verifies designs in lab environments, and maintains documentation for production hardware.
Design verification engineer leading pre-silicon verification for complex SoCs, using UVM, SystemVerilog, and formal methods to ensure correctness of AI/ML accelerators, processors, and interconnects.
Designs and verifies ASIC/FPGA chips for high-speed optical transmission systems, using VHDL/Verilog and industry tools to optimize performance and power in coherent networking hardware.
Designs and verifies ASICs and FPGAs for high-speed optical transmission systems, implementing signal processing algorithms and collaborating with global teams to optimize power and performance.
Designs and implements secure, high-performance IP blocks for Intel’s Unified Chassis, focusing on AXI/APB bridges, ECC/parity schemes, and RAS/debug telemetry for SoC reliability.
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