Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Verifies CPU logic before manufacturing by writing test benches in SystemVerilog/UVM, running simulations, debugging failures, and collaborating with architects to meet specs.
Design and verify ASIC/SoC hardware in Verilog/SystemVerilog, then evaluate and improve how AI models understand chip engineering tasks.
Design and verify FPGA modules for advanced systems, collaborating with hardware and software teams using VHDL/Verilog and Xilinx tools.
Principal FPGA engineer designing and verifying VHDL/Verilog modules for high-reliability electro-optical systems, using Xilinx tools and OSVVM/UVM testbenches.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
The NOKIA Optics Subsystems group develops the front-ends for coherent optical long-distance transmission modules to interconnect network nodes and data centers. We are expanding and looking for highly motivated and…
The NOKIA Optics Subsystems group develops cutting-edge front-end technology for coherent optical transmission modules, enabling high-speed interconnects for data centers and supporting the growing demands of AI-driven…
Design verification engineer at AMD building and maintaining test suites for next-gen CPU/DSP SoCs using SystemVerilog/UVM and scripting, ensuring functional and performance coverage.
Validate and bring up custom AI silicon from first power-on through production, testing boot, memory, interconnects, and high-speed interfaces while debugging cross-functional failures.
Let's distart! 🚀 - Schön, dass wir uns kennenlernen! Unser leistungsfähiges Team aus Leipzig hat sich der Mission verschrieben, unseren Kunden den Weg zu einem neuen beruflichen Leben zu ebnen – mit den…
Apprentice security specialist for trade-show safety, planning and executing protection measures at events in Nuremberg using basic IT skills and communication with authorities.
Design Verification Engineer builds and runs SystemVerilog/UVM testbenches to verify high-speed SerDes IP for PCIe, Ethernet, and other interfaces, debugging RTL and testbench issues.
Design verification engineer building and running UVM/SystemVerilog testbenches for AR display ICs using Siemens Questa, plus coverage closure and automation in Linux.
Senior engineer verifying next-gen mobile GPU subsystems using SystemVerilog/UVM, C++, and constrained-random testing to ensure functional correctness and performance for Samsung’s Xclipse GPU.
Design and verify ASIC/FPGA hardware for defense systems, writing RTL, running simulations, and integrating modules in a lab using Xilinx/Altera tools and scripting.
Designs and verifies FPGA hardware using VHDL/Verilog/SystemVerilog, UVM testbenches, and Xilinx tools, while guiding a remote verification team on DO-254 processes.
You lead the lifecycle of textile products, from trend analysis and design to supplier negotiations and production release, ensuring quality and sustainability in a hybrid role.
enua ist ein ganzheitlicher Hersteller für medizinisches Cannabis in Deutschland und gehört zu den Top 3 Anbietern im Markt. Unsere Vision ist es, Menschen einen nachhaltigen Zugang zu Cannabis zu verschaffen. Wir sind…
Designs and verifies digital circuits for FPGA and ASIC implementations, coding HDL modules and collaborating with cross-functional teams to meet performance and reliability targets.
Designs and implements FPGA/ASIC hardware for satellite-based 5G base stations, focusing on signal processing and power efficiency using Verilog/SystemVerilog and EDA tools.
We couldn't check your fit for this role — add a CV to your profile to see it next time.