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TE Connectivity
16 views 3 weeks ago

STAFF SYSTEM ARCHITECT

Open 56d Staff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.

Job Overview Data communications applications change at an exponential pace and the Data and Devices Business Unit is at the heart of a continuously expanding connected life. Accordingly, we provide responsive,…

Agile AI CAD Ethernet Go-to-Market +5 skills
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ams OSRAM
13 views 3 weeks ago

Principal HS Digital Design Engineer (d/m/f)

Open 56d EuropePrincipal
Italy

Principal high-speed digital design engineer at ams OSRAM in Pavia, Italy, working on digital IC design for communication and mixed-signal SoC products: RTL design in Verilog/SystemVerilog, synthesis, timing analysis, clock-domain crossing, and advanced CMOS nodes (FinFET/FD-SOI). Knowledge of UCIe/PCIe interfaces is an advantage.

Cmos PCIe Rtl SystemVerilog Verilog
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Capgemini
12 views 3 weeks ago

RTL Design Architect

Open 45d APAC
India

Capgemini is hiring an RTL Design Architect in Bangalore to lead architecture, integration, and verification strategy for high-speed connectivity IPs and chiplet interconnect solutions, defining PCIe/CXL/UCIe subsystem architecture and guiding verification teams. Requires deep expertise in PCIe Gen4/5/6, UCIe, chiplet ecosystems, and SoC integration.

AI PCIe SerDes
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Capgemini
11 views 3 weeks ago

DSP Embedded Engineer

Open 45d EuropeLead
Italy

Embedded software engineer at Capgemini Engineering in Rome developing on Texas Instruments C6000 DSP platforms (TMS320C6657) for high-performance telecom systems. Day to day: building and optimizing firmware, low-level drivers, and high-speed interfaces (PCIe) using Code Composer Studio, plus TCP3d coprocessor work.

Agile AI C++ CUDA Express.js +2 skills
28K – 40K €
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Capgemini
7 views 3 weeks ago

Ingeniero/a de Diseño de Hardware Digital y FPGA

Open 22d Europe
Spain

A digital hardware/FPGA engineer in Madrid who designs FPGA-, SoC- and microcontroller-based boards for signal acquisition and processing systems — developing complex VHDL designs for Xilinx/Intel FPGAs, integrating high-speed ADC/DAC and interfaces like PCIe and JESD204, and validating designs through simulation and lab testing.

Aurora Embedded Systems Ethernet FPGA PCIe +1 skills
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Altera Corporation
5 views 3 weeks ago

Full Chip Timing Modeling and Integration Engineer

Open 18d North America
United States

Develops timing methodologies and performs hands-on full-chip static timing analysis for Altera's next-generation FPGAs on advanced process nodes — building, integrating, and validating high-level timing models with cross-functional, multi-site design teams. Core stack: STA, Liberty/Verilog/SDC, SPICE correlation, Python/Tcl, LVF/POCV.

AI Automation FPGA Machine Learning PCIe +3 skills
133K – 193K $
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Arista Networks
4 views 3 weeks ago

FPGA Design Engineer

Open 19d HybridNorth America Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.Ireland permit employer — This employer was issued Irish employment permits this year or in the two years before, per the Department of Enterprise, Tourism and Employment. The permits belong to the employer and are not a commitment to sponsor this role.
United States

Designs and verifies control-path FPGA RTL (Verilog/SystemVerilog) for Arista's data center Ethernet switch platforms, owning the full lifecycle from architecture and board review through synthesis, timing closure, verification, and lab bring-up in collaboration with hardware, software, and manufacturing teams.

AI Arista Automation Bash Ethernet +11 skills
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Arista Networks
3 views 3 weeks ago

FPGA Design Engineer

Open 19d HybridNorth America Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.Ireland permit employer — This employer was issued Irish employment permits this year or in the two years before, per the Department of Enterprise, Tourism and Employment. The permits belong to the employer and are not a commitment to sponsor this role.
United States

Design and verify high-performance control-path FPGAs for Arista's data center Ethernet switch platforms, owning the full lifecycle from Verilog/SystemVerilog RTL development and verification through synthesis, timing closure, and system bring-up. On-site role in Santa Clara, CA requiring 5+ years of RTL design experience.

AI Arista Automation Bash Ethernet +11 skills
110K – 170K $
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Advanced Micro Devices, Inc
10 views 3 weeks ago

Senior ASIC RTL Design Engineer, AI Networking IP

Open 19d North AmericaSenior

Senior ASIC RTL design engineer on AMD's IP team building high-performance networking and communications IP cores for AMD chips. Day to day: write synthesizable Verilog/SystemVerilog RTL, leverage AI coding tools for productivity, support synthesis/timing closure, verification regressions, and emulation, and mentor junior designers.

AI Asic Atlassian Bash ChatGPT +14 skills
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HSBC Holdings plc
1 views 3 weeks ago

eTrading Full Stack Engineering - Compute

Open 19d North AmericaFull-time Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.
Canada

A hands-on compute platform engineer on HSBC's eTrading infrastructure team in Toronto, designing, qualifying and operating low-latency bare-metal RHEL servers and Docker/Podman runtimes for latency-sensitive electronic trading. Work spans BIOS/firmware and kernel tuning, hardware benchmarking, OpenSCAP hardening, SBOM supply-chain controls and automation with Ansible and Python/Java.

Ansible API Automation CI/CD Corrective Action +17 skills
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SambaNova Systems
14 views 3 weeks ago

Network Infrastructure Architect

Open 125d North AmericaFull-time Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Designs and optimizes high-performance networks for AI compute clusters, focusing on InfiniBand, RoCE, spine-leaf architectures, and 400G/800G interconnects to support next-gen AI workloads.

Agentic AI AI Automation BGP Ethernet +10 skills
250K – 330K $
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SambaNova Systems
10 views 3 weeks ago

Senior Hardware Design Engineer

Open 71d North AmericaFull-timeSenior Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Designs and owns RTL blocks for SambaNova’s AI-accelerating RDU ASICs, shepherding them from spec to silicon bring-up while optimizing for power, performance, and area.

Agentic AI AI Asic Automation Bash +11 skills
120K – 200K $
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Advanced Micro Devices, Inc
8 views 3 weeks ago

IOHUB Design Verification Engineer

Open 19d North America

Design Verification Engineer on AMD's NBIO team, defining and executing verification for the IOHUB Core (PCI host bridge) and IOMMU IP blocks. Day to day: writing test plans and UVM/SystemVerilog components, and driving coverage-based verification closure for interconnect IP used in GPUs, APUs, servers, and game consoles.

AI Machine Learning PCIe SystemVerilog Uvm +2 skills
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STR
12 views 3 weeks ago

Lead Digital Hardware Engineer

Open 19d North AmericaFull-timeLead
United States

STR's Space Missions and Sensing sector is hiring a Lead Digital Hardware Engineer in Woburn, MA to design, integrate, and test high-speed digital circuit cards and modules for radar, electronic warfare, and space-based sensing prototypes. The role leads small engineering teams using FPGA/SoC-based board design, Altium, high-speed interfaces (PCIe, SerDes, DDR), and signal/power integrity analysis

Altium Analytics CAD Ethernet FPGA +8 skills
174K – 225K $
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Nuro Backed by GreylockBacked by SoftBank Vision Fund
10 views 3 weeks ago

Principal Software Engineer, Onboard Infrastructure

Open 134d North AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Software Engineer leads the design and development of Nuro’s onboard infrastructure for autonomous vehicles, focusing on hardware-agnostic device interfaces, runtime systems, and distributed execution to ensure high-performance, reliable autonomy software across platforms.

AI API C++ CUDA Data Pipelines +13 skills
258K – 387K $
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Alibaba Group
1 views 3 weeks ago

阿里云智能-服务器BIOS开发工程师-深圳/杭州

APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
China

1、负责服务器BIOS 自主研发及产品交付和维护，能主导需求分析、版本管理、功能开发与测试，线上运维全生命周期研发，保障产品高质量交付。 2、负责海量服务器硬件组件的BIOS 统一化定制， 与厂商协同研发并指导其开展工作，推动 BIOS 研发标准化，测试自动化。 3、负责服务器BIOS/CPU领域RAS、故障定位系统、系统性能调优、安全、功耗等竞争力特性的策略制定、方案落地。…

AI GPU PCIe
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CLOCK EDGE TECHNOLOGIES
3 weeks ago

Senior Manager - Characterization

APACSenior
India

About this Position : The candidate will lead the characterization team to support the rollout of the next generation products to the market. This cross functional role will involve leading the work of a team and will…

Cmos C++ Firmware FPGA Java +9 skills
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MTC Consulting Pte. Ltd.
7 views 3 weeks ago

Senior Software Engineer – Python-based GUI / Test Automation

Open 19d LATAMSenior
Brazil

Senior software engineer who builds Python-based desktop applications and test automation software for silicon photonics chip and optical component testing. Day to day involves developing PyQt/PySide GUIs, instrument-control and data-acquisition tools, MySQL test-data databases, and hardware interfaces such as Ethernet, SPI and PCIe.

API Automation C++ Data Visualization Ethernet +9 skills
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ByteDance
7 views 3 weeks ago

芯片软件研发工程师（存算与AI） - 芯片研发

APACJunior
China

团队介绍：字节芯片研发团队目前工作主要集中在芯片设计环节，主要围绕字节自身业务展开芯片探索，为字节多项业务的专用场景定制硬件优化，设计多款基于先进半导体工艺的云端复杂芯片，以期提升性能、降低成本。早期若干芯片项目已经进入到量产部署阶段，有多次一版成功的投片经历，所用工艺包含多个主流的先进工艺节点。与基础设施各团队之间工作的整体协同，能更容易和更好地发挥芯片研发的价值。 1、负责芯片验证与软件功能的方案设计、编码、测试、联调等工作；…

I2c Linux PCIe
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ByteDance
4 views 3 weeks ago

高速接口资深驱动工程师（存算与AI） - 芯片研发

APACSenior
China

团队介绍：聚焦存算一体芯片设计，主要围绕AI大模型应用场景进行高能效计算技术创新，设计多款基于存算一体架构的高能效AI芯片，突破传统冯・诺依曼架构下的 "内存墙" 瓶颈，提升能效比、降低算力成本。团队具备独立流片与量产落地能力，累计申请专利近300项，核心专利覆盖“底层器件-核心架构-工程落地”全流程。同时与字节各团队算力需求整体协同，更好的发挥存算一体芯片的技术价值，共同为AI业务提供高能效算力底座。…

PCIe SerDes
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