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Designs and integrates FPGA firmware for next-gen combat aircraft systems, using VHDL/Verilog and embedded systems while collaborating on cutting-edge defense technology.
Leads timing design for high-performance SoC chips used in automotive electronics, using static timing analysis, synthesis, and global collaboration with overseas teams.
Designs and verifies memory controller silicon IP in Verilog/SystemVerilog, integrates third-party IP, and provides customer support in Hillsboro, OR.
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most…
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Date Posted: 2026-07-17

 Country: United States of America

 Location: US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG

 Position Role Type:…
Job Description Revelyst, is a collective of makers who design and manufacture performance gear and precision technologies. Our category-defining brands leverage meticulous craftsmanship and cross-collaboration to…
Principal Engineer leading ASIC design implementation from RTL to GDS, optimizing flows and guiding teams in synthesis, timing signoff, and low-power techniques for advanced process nodes.
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Designs and runs verification tests for custom silicon chips used in data centers, using hardware verification languages like SystemVerilog and UVM.
We are seeking great talent to help us build The DNA of tech.® Vishay manufactures one of the world's largest portfolios of discrete semiconductors and passive electronic components that are essential to innovative…
Designs and simulates FPGA-based wireless IP using Verilog/VHDL, focusing on RTL coding, synthesis, and timing analysis for next-generation solutions.
Designs and implements RTL logic for complex SoCs, integrating IP and writing Verilog/SystemVerilog code while collaborating with verification and performance teams in Bangalore.
Designs and implements CPU components like interconnects and caches using Verilog and ASIC flow, collaborating with verification and implementation teams to meet performance and power goals.
Develops and validates firmware for next-generation SmartNIC networking devices, focusing on congestion control, virtualization, and QoS using C and embedded systems.
Engineer designs and develops precision digital hardware using System Verilog, Verilog, or VHDL, and CAD tools like Altium Designer in a Russian precision instrument manufacturing firm.
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
About Graphcore At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software…
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