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Senior Antenna Hardware Engineer
Hands-on senior individual contributor who owns the phased-array antennas and RF receive chains on Hubble's satellites — defining array architecture, running EM simulation, executing Altium PCB layout, and leading antenna/RF characterization for the company's direct-to-satellite Bluetooth IoT network. Hybrid role based in Seattle.
FPGA Engineering Intern - Summer 2027
HPR (Hyannis Port Research) builds ultra-low latency electronic trading and capital markets infrastructure as a managed service. This summer internship has you own an FPGA project through its full development life cycle and build tools that automate RTL and testbench generation, using Verilog/VHDL plus scripting languages like Python.
Hardware Engineer
Hardware Engineer at Rincon Research Corporation designing digital signal processing hardware for US Defense and Intelligence customers. Day to day: circuit design, schematic capture, PCB layout, test development, and manufacturing support, working with RF/high-speed digital electronics and FPGA-based systems onsite in Tucson, AZ.
Advanced System Engineer
Why Join Rincon Research Corporation (RRC)? At Rincon Research Corporation, our primary business is innovating, developing, and fielding digital signal processing (DSP) products and services for the United States…
Marketing Manager, Broadcast & ProAV
About Macnica Macnica Americas, Inc. is the North American division of Macnica Fuji Electronics Holdings, Inc. a $10 billion technology solutions provider with a stronghold in semiconductor distribution. Macnica excels…
Embedded Software Engineer, Tampere
About the role In this position, you will be responsible for designing, developing, and verifying embedded software used in power electronics applications. You will own the full software development lifecycle—from…
Senior Design Verification Engineer
Senior Design Verification Engineer on Microsoft's custom silicon team (Azure Cobalt), verifying custom IP at block and sub-system level across pre-silicon (UVM simulation, emulation, FPGA) and post-silicon validation. Core stack: UVM, C/C++ testbenches, silicon bring-up, coverage closure, and formal verification with Jasper.
