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Lead analog design for high-speed Serdes transceivers, defining circuits and supervising teams to deliver silicon-validated IP for interfaces like PCIe and UCIe using advanced CMOS processes.
Designs and automates verification environments for AI accelerator IP blocks using UVM, SystemVerilog, and C/C++, ensuring functional and performance validation.
Lead accounting operations for Samsung’s U.S. semiconductor sales and R&D entity, ensuring IFRS/US GAAP compliance, financial reporting, internal controls, treasury, and AP while partnering with HQ in Korea.
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Builds and automates verification environments for AI accelerator IP blocks using UVM, SystemVerilog, and C/C++ to ensure functional and performance correctness.
Lead OCP S.A.F.E. certification for Samsung’s enterprise SSDs, coordinating security reviews, vendor management, and cross-team engineering to deliver compliant storage solutions.
Develops firmware for next-gen memory solutions like HBM, working with ARM cores, RTOS, and hardware bring-up while collaborating with cross-functional teams.
Manages daily treasury operations, cash forecasting, and banking administration for a global semiconductor company, ensuring liquidity and compliance.
Design low-power analog and mixed-signal Serdes circuits (USB, PCIe, UCIe) for high-speed interconnects using advanced CMOS processes and validate them in silicon.
Design high-speed I/O interfaces for Samsung’s AI SoCs, focusing on chiplet die-to-die links and PHY IP while collaborating with analog and system teams.
Senior Staff Engineer leads the design and optimization of EDA (Electronic Design Automation) environments and large-scale compute infrastructure for Samsung Semiconductor’s semiconductor design teams, ensuring productivity and cost efficiency through standardization, vendor management, and infrastructure roadmapping.
Build and deploy agentic AI systems for semiconductor design workflows, optimizing LLM inference and multi-agent orchestration on large-scale compute infrastructure.
Senior Physical Design Engineer responsible for physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII, including synthesis, floorplanning, placement, clock tree synthesis, and routing. Core technologies include EDA tools like Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC, with expertise in timing closure, low-power design, and s
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