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Design and verify FPGA-based prototypes for Intel’s IP blocks, integrating and debugging RTL designs to enable early hardware and software validation.
Leads architecture and design of next-gen high-performance test platforms, focusing on high-speed digital, signal/power integrity, and system integration for memory validation systems.
Nova's Materials Metrology Division is looking for a skilled Firmware Engineer (Embedded) to design, develop, and test firmware and software for our core hardware platforms. The engineer will collaborate closely…
Designs ultra-low-latency FPGA-based systems for real-time trading acceleration using RTL and hardware design, working alongside experts in a research-driven finance firm.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Drive product planning and strategy for next-generation FPGA and Adaptive SoC platforms, translating customer needs and market trends into product requirements and roadmap decisions.
Senior engineer verifying complex processor designs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness of Network-on-Chip IPs and SoCs.
Design and verify electrostatic discharge (ESD) protection circuits for advanced ASIC and FPGA chips using SPICE, PDKs, and EDA tools like Cadence Virtuoso.
Develop embedded C/C++ software and Linux platform support for AMD Adaptive SoCs and Ryzen AI Embedded processors, building computer vision, graphics, and edge AI pipelines for robotics and industrial automation.
Build embedded, cloud, or AI software for automotive systems and digital platforms at Bosch’s Vietnam R&D center, working on ECUs, ADAS, cloud services, and enterprise tools.
Design analog and digital circuits for automotive diagnostic tools, verify hardware designs, and manage product changes for Bosch’s aftermarket repair solutions.
Designs and optimizes advanced semiconductor IP and SoCs from RTL to GDSII, focusing on timing closure, power reduction, and physical verification for next-gen FPGAs.
Senior engineer who implements custom IP and SoC designs from RTL through GDSII, closing timing, optimizing power, and signing off on next-gen FPGA silicon using Synopsys/Cadence EDA tools.
Build and optimize inference systems for AI models powering trading decisions, focusing on GPU kernels, FPGAs/ASICs, and data streaming to maximize performance in a high-impact, research-driven environment.
Build and optimize large-scale AI model training systems (kernels, data loading, parallelism) for HRT’s trading-focused foundation models, working closely with researchers to improve performance and impact.
Designs and optimizes FPGA/ASIC hardware for low-latency trading systems using SystemVerilog, RTL, and vendor tool suites.
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