Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Senior PCB Design Engineer at Arista Networks designing ultra-high-speed, 20-30+ layer boards for 800G/1.6T networking platforms — routing 112G/224G SerDes, PCIe Gen5/6 and DDR interfaces, optimizing signal/power/thermal integrity, and taking products from concept through mass production using Cadence Allegro and Sigrity.
Develops and maintains C++ device drivers for autonomous truck sensors, integrating hardware interfaces and optimizing real-time performance in Linux environments.
Senior Lab Systems Engineer at AMD who deploys, maintains, and debugs next-gen HPC and AI server/rack-scale platforms in a Rockdale, Texas lab datacenter. Daily work spans hardware installation, root cause analysis across hardware, firmware, OS, and networking layers, plus Linux administration and Python/Bash/C/C++ scripting for automation.
Principal Product Manager owning the strategy, roadmap, and commercial execution for passive optical fiber-connectivity products in rack-scale AI infrastructure at Astera Labs. The role sets customer-driven requirements with hyperscalers, drives products from concept through qualification and production ramp, and spans optics, co-packaged/near-package optics, manufacturing, supply chain, and go-to
Senior Hardware Engineer designs, deploys, and troubleshoots high-performance GPU-based cloud systems for AI workloads, focusing on compute, networking, and server infrastructure.
Designs and verifies custom silicon for autonomous vehicles, using UVM/SystemVerilog to validate hardware functionality and performance in a hybrid work environment.
Develops and maintains Linux kernel drivers and embedded system software for Waymo’s autonomous vehicle compute platform, working with custom hardware like ASICs and FPGAs.
Develops and optimizes firmware, drivers, and compute architectures for Waymo’s high-performance autonomous vehicle hardware, focusing on AI workloads and custom silicon.
Senior Embedded Software Engineer at the Rivian–Volkswagen joint venture building software for design verification of automotive PCBAs and ECUs across vehicle platforms (autonomy, infotainment, vehicle controls). Day to day involves writing device drivers, hardware/software co-design prototypes, and Python/C validation tests on Linux and RTOS, plus board bring-up and debugging with tools like JTAG
Role Summary As a Lead System Architect at Axiado, you will define the end-to-end architecture bridging silicon (ASIC/SoC), board-level hardware platforms, and low-level system software/firmware. Leveraging your deep…
Owns the Linux mission computer for Mach Industries' autonomous defense platforms: bringing up Jetson-class boards (BSPs, device trees, kernels), integrating cameras and sensors via MIPI CSI/V4L2 and SerDes, and building the real-time sensor-to-GPU pipeline that runs perception and on-target CUDA/TensorRT inference under SWaP, thermal, and vibration constraints.
About IonQ: IonQ, Inc . [NYSE: IONQ] is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation…
Designs and delivers high-reliability electronics for spaceflight systems, leading full-cycle PCB design from concept to flight readiness while collaborating with cross-functional teams.
Senior Hardware Systems Engineer who designs, validates, and deploys Verra Mobility's hardware/firmware systems — especially camera, radar, and embedded sensing devices — while managing field failure analysis and 3rd-party ODM acceptance testing. Core tech includes Cadence/Allegro PCB design, lab instrumentation, signal integrity, and firmware configuration.
Hardware Applications Engineer at Xsight Labs working hands-on with customers designing boards around the company's X2 switch and E1 DPU silicon: running schematic and PCB layout reviews, high-speed signal/power integrity analysis, test planning, and post-sales support. Requires 8+ years of high-speed PCB design experience.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Eridu AI is hiring a senior SerDes software engineer to lead bring-up, validation, and optimization of high-speed interfaces (224G PAM4 Ethernet, PCIe, UCIe chiplet interconnects) in advanced networking and compute silicon. Day to day, they'll write embedded C/C++ firmware and Python tooling for PHY initialization, link training, equalization, calibration, and diagnostics, working closely with ana
Principal-level hardware systems engineer at Pure Storage defining next-gen enterprise and cloud-scale storage platforms: owns the multi-generational hardware roadmap, leads JDM/ODM design reviews and validation strategy, drives Python/Bash test automation, and is the final escalation point for complex hardware failures. Core tech: x86/ARM, PCIe Gen 5/6, CXL, NVMe-oF, BMC/Redfish/IPMI.
Principal System Validation Engineer at Astera Labs designs and runs automated tests for AI fabric switches, ensuring compliance with high-performance requirements for data center AI/ML systems using PCIe, CXL, Ethernet, and related protocols.
A consultancy is hiring an experienced FPGA / Digital Design Engineer in Sweden (on-site/hybrid) to design high-speed, multi-clock FPGA systems: writing RTL in VHDL/SystemVerilog, handling clock domain crossings, and implementing designs with Xilinx Vivado and Intel Quartus across the full FPGA lifecycle.
We couldn't check your fit for this role — add a CV to your profile to see it next time.