Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Design and implement CPU microarchitecture and RTL for high-performance, low-power devices, collaborating with architects and verification teams.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Semiconductor innovation is accelerating faster than ever, driven by AI, advanced computing, automotive…
Description Senior Software Engineer (Full Stack) Location: Farnborough or Whiteley, with flexibility to work from home dependent on business demands Salary: £61,500 - £78,800 The Role: As a Senior Software Engineer…
Designs and verifies analog and mixed-signal ICs to emulate obsolete microcircuits for defense systems, using tools like Verilog/VHDL and Python.
Analyzes and optimizes radar system performance for missile warning radars, reducing track data, diagnosing anomalies, and refining operational procedures to ensure mission readiness.
Designs and runs automated and manual tests for embedded storage software, writes test plans in C/C++, and tracks bugs in JIRA to ensure product quality.
As a Capital One Director of Software Engineering, youll work on everything from customer-facing web and mobile applications using cutting-edge open source frameworks, to highly-available RESTful microservices, to…
Architect next-generation pre-silicon verification strategies for complex semiconductor designs, leading simulation, formal, and emulation methodologies to ensure first-pass silicon success.
Designs high-speed VLSI circuits for next-gen CPU cores and caches using deep submicron FinFET processes, optimizing power, performance, and area while collaborating across teams.
Lead a team to implement and tape out high-performance ASIC/APU/dGPU designs for AI, gaming consoles, and automotive using RTL-to-GDS flows, PnR, timing closure, and physical verification.
Senior engineer verifying complex processor designs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness of Network-on-Chip IPs and SoCs.
Lead end-to-end delivery of firmware infrastructure for AMD’s CPUs/GPUs, including design, validation, and CI/CD automation in C/C++ and cloud environments like Azure and Kubernetes.
Designs and verifies custom IC layouts for analog and digital circuits using Cadence Virtuoso and Mentor Calibre, including PLLs, DACs, and high-speed signaling blocks.
Intern develops embedded C/C++ software for microcontrollers on Linux-based systems, integrating and testing modules for Bosch’s global projects.
Internship role automating software engineering workflows using Python, Jenkins, and CI/CD pipelines for embedded systems at a global tech supplier.
Designs and verifies GPU and control subsystems for AI-focused SoCs, integrating Arm IP and third-party components for edge, physical, and cloud AI applications.
Build and optimize electronic design automation tools and flows for semiconductor teams using Python and AI-assisted scripting to improve design efficiency and time-to-market.
Designs and optimizes advanced semiconductor IP and SoCs from RTL to GDSII, focusing on timing closure, power reduction, and physical verification for next-gen FPGAs.
Senior engineer who implements custom IP and SoC designs from RTL through GDSII, closing timing, optimizing power, and signing off on next-gen FPGA silicon using Synopsys/Cadence EDA tools.
Lead a team to design and deliver embedded memory compilers (SRAM, ROM, register files, DPRAM) across process nodes, setting technical direction and driving PPA optimization while serving as the senior technical voice in customer engagements.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
