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Design Verification Engineer at AMD responsible for verifying custom hardware accelerators for servers, datacenters, and client/embedded markets using advanced ASIC verification techniques and methodologies like UVM and formal verification.
Build and maintain global log and monitoring infrastructure for financial markets tech, using APM tools like Datadog and Splunk to track network and app anomalies across data centers.
Senior Software Engineer building and maintaining Java-based web applications for a government cybersecurity team with active TOP SECRET/SCI clearance.
Designs and lays out CMOS and metallization test structures for semiconductor R&D, using EDA tools like Cadence Virtuoso and Calibre to enable DRAM/NAND process development and reliability analysis.
Design and automate physical verification flows for semiconductor scribe designs, coding rule decks in Calibre SVRF/TVF and scripts in Python/Perl to validate PDK updates and IC layout.
Design Verification Engineer at NXP Semiconductors in Catania; builds and runs UVM/SystemVerilog test benches to validate complex semiconductor designs.
Junior engineer verifying semiconductor designs using SystemVerilog, UVM, and simulation tools to ensure functional correctness and reliability.
Build and maintain full-stack manufacturing applications using C#, .NET, and cloud services, while leveraging AI tools to improve code quality and productivity.
Build and maintain CI/CD pipelines and automation for Mastercard’s BizOps team to improve reliability, deployment, and incident response in a large-scale fintech environment.
DMTS, DRAM Systems Location: San Jose, CA, Folsom, CA Time Type: Full time Job Description Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in…
Design and run verification testbenches for DRAM memory blocks using SystemVerilog/UVM, analyze coverage, and debug failures to ensure tapeout readiness.
Architect GPU performance by analyzing bottlenecks in high-end SoCs and GPUs, modeling hardware at multiple abstraction levels, and optimizing for graphics, ML, and automotive workloads.
Architect and implement firmware for reliability, availability, serviceability, and power management across NVIDIA’s networking platforms, collaborating with hardware, software, and validation teams.
Design-for-Test Engineer at NVIDIA develops test architectures and methodologies for complex semiconductor chips, including scan compression, memory/IO BIST, and post-silicon validation.
A Mission Planner/Orbital Analyst supports experimental satellite systems, performing pre-launch and on-orbit mission planning, interfacing with payload customers, and developing mission documentation, using orbital mechanics and scripting languages like Python and C++.
Analyzes and validates cybersecurity vulnerability reports for a DoD customer, using tools like Kali Linux and Burp Suite to assess risks and recommend mitigations.
System Engineer with DNS knowledge (IoT) (m/f/d) Location: Madrid, MD, es, Remote Company Description T‑Systems is part of the Deutsche Telekom Group, with around 30.000 employees worldwide. We create technology with…
Build and maintain scalable Java/Scala systems for risk analytics and trading infrastructure, partnering with traders and quants to deliver high-performance distributed solutions.
Designs and develops FPGA-based hardware solutions for aerospace/space equipment using VHDL, ensuring compliance with strict space industry constraints like radiation resistance and thermal management. Leads technical trade-offs, algorithm-to-hardware translation, and full lifecycle validation (simulation, synthesis, P&R, testing).
Designs and implements advanced chip pad rings and package layouts for AI hardware, collaborating with cross-functional engineering teams to optimize electrical performance.
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