Tech jobs
Job listings
Physical Design Student
Student role assisting senior engineers with physical design tasks for cutting-edge AI semiconductor chips, including synthesis, floorplanning, and verification using industry-standard EDA tools.
Principal Physical Design Engineer, STA
Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.
Applications Engineering Manager - Ethernet
Principal Product Applications Engineer at Astera Labs designs and troubleshoots high-speed Ethernet connectivity for AI infrastructure, working directly with customers to deploy Taurus Smart Cable Modules in data centers.
Principal Silicon Validation Engineer
Principal Silicon Validation Engineer at Astera Labs in San Jose, CA designs and executes electrical tests to validate AI connectivity hardware, using PCIe, Ethernet, and CXL technologies.
Principal ATE Test Engineer
Principal Test Engineer at Astera Labs designs and implements automated test solutions for high-speed mixed-signal silicon SoC products, using protocols like PCIe, Ethernet, and DDR, and oversees production ramp.
Senior Design Verification Engineer
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
Senior Embedded Software Engineer - Ethernet Retimers
Develops and debugs firmware for Ethernet retimers in AI infrastructure, troubleshooting link failures and integrating new products from silicon bringup to deployment.
Senior Principal Engineering Program Manager
Leads end-to-end execution of advanced-node ASIC products from concept to production, managing schedules, budgets, and cross-functional teams to deliver revenue-critical silicon on time and at scale.
Staff/ Principal Chip Top Physical Design Engineer
Designs and implements top-level physical design for AI-focused semiconductor chips, collaborating with cross-functional teams to meet strict performance, power, and area targets.
Staff Physical Design Engineer - SoC EMIR Engineer
Designs power integrity and electromigration checks for AI-focused semiconductor chips, using tools like Ansys RedHawk and Cadence Voltus to ensure reliability in advanced FinFET nodes.
Principal Architect
Principal Architect at Astera Labs in Tel Aviv designs high-performance AI connectivity solutions, focusing on PCIe, Ethernet, and advanced interconnect protocols like CXL and UALink.
Staff/ Principal Design Verification Engineer
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Senior Director, Corporate Development
Leads strategic transactions like acquisitions and partnerships for a semiconductor company specializing in AI connectivity solutions, working with leadership to shape growth in rack-scale AI infrastructure.