Senior physical design engineer who owns end-to-end implementation of complex mixed-signal SoC blocks — synthesis, place-and-route, static timing analysis, and physical verification — integrating digital, custom analog, and photonics components for Ayar Labs' co-packaged optics interconnects for AI. Core tooling includes Cadence/Synopsys flows (Genus, Innovus, ICC) plus DFT and scripting.
Sign in to see your match