Senior Design Verification Engineer on Capgemini Engineering's expanding Ukraine VLSI team: owns IP/SoC verification from RTL through emulation, defines and improves DV methodology, and builds UVM-based testbenches. Core stack is SystemVerilog, UVM/OVM, protocol knowledge (AHB/AXI, PCIe, USB, DDR) and Perl/TCL/Python scripting.
Sign in to see your match