Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at…
The candidate is expected to be responsible for following tasks: Participate in complex Chip DFT/DFD feature and architecture definition Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test…
Annapurna Labs designs the custom silicon and systems at the heart of AWS (Amazon Web Services). Here you'll move like a startup, build at the scale of the world's largest cloud, and push the limits of what…
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
Designs and implements RTL code and micro-architectures for digital IPs and SoCs in the automotive domain, following the full ASIC flow.
SignOff Semiconductors is hiring a Senior Design Verification Engineer in Bangalore to lead ASIC/SoC/IP verification projects for global semiconductor customers. The role involves defining verification plans, building UVM/SystemVerilog testbenches, and driving simulation, regression, debugging, and coverage closure.
Architects SoC networking engines, SmartNIC/NIC designs, and interconnect fabrics for custom AI servers at a US-Israeli startup in Raanana: defining scale-up/scale-out topologies, RDMA/RoCEv2 transport offloads, and hardware acceleration of AI collective operations, collaborating across silicon, firmware, and software teams.
Crane Aerospace and Electronics has an exciting opportunity for an Electrical Engineer II at our Lynnwood, WA location. About Crane: Crane Aerospace & Electronics supplies critical systems and components to the…
Job Description: Our company is seeking a Specialist, FPGA Verification for our Tactical Communications business within our Communication Systems segment. The successful candidate will function primarily in an FPGA…
Full-cycle technical recruiter for Normal Computing's silicon organization, sourcing and closing senior hardware, ASIC, and silicon architecture engineers (often passive candidates) out of Mountain View. The role leans on semiconductor domain fluency, deep partnership with engineering hiring managers, WHO Method calibration, and Ashby ATS ownership.
Technical Recruiter for ASIC and silicon roles at an AI-native semiconductor startup, owning full-cycle recruiting for chip architects, RTL and DV engineers, and physical design while partnering directly with engineering hiring managers to close top talent against competing offers.
For more than 60 years, Power Device Corporation (PDC) has been recognized as a world leader in the design and manufacture of high-reliability Connectivity, Power, and Control solutions for the Aerospace, Defense, and…
ABOUT RISHIHOOD UNIVERSITY Rishihood is India's first national transformation university. It prepares learners to solve the big problems of tomorrow. Our transformative education is built on three pillars: •…
Senior FPGA engineer who designs and verifies RTL in Verilog/VHDL, builds self-checking test benches and simulations (Synplify Pro, ISE, Vivado, Libero), debugs hardware in the lab with scopes and logic analyzers, and leads/mentors a small engineering team. Requires 10+ years of FPGA experience and US citizenship.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop innovators and leaders who want to make an impact on the world of…
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most…
Hardware Engineer specializing in RTL/PD, optimizing designs from microarchitecture to tapeout for AI-native ASICs at Normal Computing, a deep-tech semiconductor startup.
Leads day-to-day DFT architecture and execution for Astera Labs' high-speed PCIe and Ethernet signal-conditioning chips used in rack-scale AI infrastructure. Day to day: defining test strategies (scan, ATPG, MBIST, JTAG), driving tape-out and production ramp, improving yield and diagnostics, and mentoring DFT engineers.
Leads front-end digital design of PCIe/CXL, UALink, and Ethernet connectivity silicon for rack-scale AI infrastructure, owning the full chip lifecycle from requirements and RTL through verification, tape-out, and shipment while managing and mentoring a team of 6-8 digital design engineers.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
We couldn't check your fit for this role — add a CV to your profile to see it next time.
