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Summer 2027 hardware engineering internship at Hudson River Trading, where interns design and verify FPGA/ASIC compute engines for low-latency algorithmic trading — writing SystemVerilog design code and Python-based modeling/verification environments on critical, real-time trading infrastructure.
Solidigm is currently seeking Firmware and Embedded Software Design professionals to join a growing team working on next generation Solid State Disk (SSD) solutions within our Non-volatile Memory Solutions Group. In…
The FPGA Verification Engineer will design and execute verification environments for imaging systems using SystemVerilog, UVM, and VHDL. This role involves leading verification efforts, creating test plans, and collaborating with interdisciplinary teams to mature prototypes into defense products.
Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology…
Define custom silicon architectures for next-gen Oura wearable health products, balancing power, size, cost, and performance while collaborating with internal teams and semiconductor vendors.
The Silicon Product & Test Engineer will manage the post-silicon productization of bitcoin mining ASICs, overseeing everything from bring-up to high-volume manufacturing. The role involves silicon characterization, yield optimization, and developing ATE test strategies using tools like Python and ATE platforms.
Design Verification Engineer builds and runs testbenches for FPGA/ASIC hardware used in low-latency trading systems, using SystemVerilog, UVM, and open-source tools like Verilator and Cocotb.
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…
Principal ASIC/SoC Architect role on an international project building ASICs for high-volume, cost-sensitive electronics. You drive the full chip lifecycle — architecture and technology selection, third-party IP integration, foundry/OSAT collaboration, tape-out, manufacturing, test, and yield optimization — with regular travel to Denmark.
Leads DSP system architecture for high-speed optical transceivers (800G/1.6T+), optimizing algorithms like equalization and clock/data recovery while collaborating with hardware/photonics teams to design next-gen optical chips.
We are looking for an enthusiastic UFS Design Verification Engineer with 7–8 years of proven professional experience to join our IP Design team. As a UFS Design Verification Engineer, you will be part of a highly…
We are looking for an enthusiastic PCIe Design Verification Engineer with 7–8 years of proven professional experience to join our IP Design team. As a PCIe Design Verification Engineer, you will be part of a highly…
We are looking for experienced Physical Design Engineers with 7–8 years of proven professional experience to join our IP Design team. As a Physical Design Engineer, you will be part of a highly competent team…
We are looking for an enthusiastic UAL Design Verification Engineer with 4–5 years of proven professional experience to join our IP Design team. As a UAL Design Verification Engineer, you will be part of a highly…
Own verification of FPGA/SoC designs for flight-critical avionics using SystemVerilog and UVM methodology on AMD (Xilinx) platforms.
Senior FPGA Verification Engineer at Anduril (Costa Mesa, CA) owns UVM-based, coverage-driven verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics. Core tech: SystemVerilog, UVM, SVA, simulators like Questa/VCS/Xcelium/Vivado, with DO-254 safety standards.
Leads ASIC physical design for Cisco’s networking hardware, optimizing chip layouts, managing cross-functional teams, and driving SoC execution from concept to release in advanced process nodes.
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
Date Posted: 2026-09-03

 Country: United States of America

 Location: US-TX-MCKINNEY-513WC ~ 2501 W University Dr ~ WING C BLDG

 Position Role Type:…
Date Posted: 2026-09-03

 Country: United States of America

 Location: US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG

 Position Role Type:…
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