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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is a great opportunity for a strong technical engineer to join a highly skilled Application Engineering…
Field Application Engineer working at the intersection of integrated photonics and scientific AI: partnering with customer photonics teams to architect AI-assisted workflows for PIC design, simulation, tapeout, and yield analysis on the Axiomatic Intelligence platform. Core tools include PIC EDA software (COMSOL, Ansys, RSoft, Cadence, Synopsys, Luceda) plus Python.
Job Details: Job Description: The Role and Impact As a Layout Design Engineer, you will play a critical role in the physical implementation of next-generation high-performance Intel Atom microprocessors. Your…
Designs high-speed analog driver and TIA chips (100G–400G per lane) for Alibaba DAMO Academy's advanced optical interconnects (NPO/CPO/OIO): architecture and transistor-level design, low-noise broadband amplification, co-design with photonic chips and photodetectors, EM/packaging parasitic extraction, plus lab characterization and BER testing. Key stack: SiGe BiCMOS, Cadence Virtuoso/Spectre/Calib
We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company…
We are seeking a highly motivated Memory Layout Engineer with strong expertise in custom layout development for advanced memory compilers. The ideal candidate will have hands-on experience in SRAM/MRAM layout design,…
A customer-facing product engineer at Cadence driving the development and adoption of advanced backend (physical design) flows in the Virtuoso custom IC platform for leading-edge process nodes. Day to day: automate layout/signoff with SKILL, Python, Perl or shell, troubleshoot with R&D, and support chip-design customers.
Principal Analog Design Engineer who architects and designs high-speed analog/mixed-signal circuits (PLLs, SerDes building blocks, ADCs/DACs, references, clocking) for Astera Labs' AI connectivity silicon, owning designs from spec through layout and silicon bring-up in advanced FinFET nodes, using Cadence Virtuoso/Spectre and mentoring the analog team.
Hands-on principal-level analog IC designer at Astera Labs who architects high-speed analog/mixed-signal circuits (PLLs, SerDes, ADCs/DACs, clocking) for AI infrastructure connectivity silicon in advanced FinFET nodes, owning designs from spec through silicon bring-up while setting methodology and mentoring the analog team in San Jose.
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve…
If you have any questions, please contact the recruiter: Melissa Kissinger Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology…
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