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VLSI Design Engineer responsible for designing cutting-edge communication systems from scratch, including micro-architecture definition, RTL coding in Verilog/SystemVerilog, synthesis, timing analysis, and PPA optimization, collaborating closely with verification, DFT, and physical design teams.
Job Details: Job Description: The Role and Impact As a GPU Logic Design Engineer, you will contribute to the design and validation of cutting-edge graphics IPs, including compute, display, and media units. You will be…
RTL Design Engineer at AMD working on SOC integration for IO peripheral subsystems (UFS, SDIO, Octal SPI) targeting ARM/RISC-V processor systems. Requires 4-5 years of RTL design experience, expertise in protocols like AXI, processor, interconnect, and microarchitecture design for semiconductor products.
The candidate is expected to be responsible for following tasks: Participate in complex Chip DFT/DFD feature and architecture definition Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test…
NVIDIA's MSS-Interconnect frontend team is looking for an intern to help explore where modern AI can create real value for RTL, verification, debug, and design-review workflows. During your internship, you will…
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
Designs and implements RTL code and micro-architectures for digital IPs and SoCs in the automotive domain, following the full ASIC flow.
SignOff Semiconductors is hiring a Senior Design Verification Engineer in Bangalore to lead ASIC/SoC/IP verification projects for global semiconductor customers. The role involves defining verification plans, building UVM/SystemVerilog testbenches, and driving simulation, regression, debugging, and coverage closure.
Leadership role owning ASIC/SoC physical design and timing signoff at SignOff Semiconductors in Bangalore: building and mentoring physical design/CAD teams, driving full-chip implementation (floorplanning, placement, CTS, routing), and signoff closure (STA, IR/EM, DRC/LVS, UPF/CPF) using Synopsys/Cadence EDA tools. Requires 12-20 years' experience with 2+ years in senior management.
Leads end-to-end ASIC physical design for advanced-node SoCs at a secure-microelectronics company — owning the flow from RTL handoff, floorplanning, and place-and-route through CTS, timing/power sign-off, and tapeout using Cadence/Synopsys EDA tools, while mentoring junior physical designers.
Junior Digital Design Engineer at Samsung's Israel R&D Center (SIRC) Memory team in Tel Aviv, working on flash memory products: designing IPs from architecture definition through RTL implementation to tape-out, including micro-architecture planning, RTL coding, simulation/debug, and sign-off for timing, area, and power.
Quantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing…
ABOUT RISHIHOOD UNIVERSITY Rishihood is India's first national transformation university. It prepares learners to solve the big problems of tomorrow. Our transformative education is built on three pillars: •…
Senior FPGA engineer who designs and verifies RTL in Verilog/VHDL, builds self-checking test benches and simulations (Synplify Pro, ISE, Vivado, Libero), debugs hardware in the lab with scopes and logic analyzers, and leads/mentors a small engineering team. Requires 10+ years of FPGA experience and US citizenship.
The application window is expected to close on: 10/22/2026 Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products…
Staff-level hardware Design Verification engineer at Cerebras Systems, ensuring the company's wafer-scale AI chip works on first silicon: building UVM/SystemVerilog testbenches, coverage plans and regression flows, and debugging issues across simulation, emulation, and silicon bring-up. On-site in Sunnyvale, CA.
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most…
Entry-level digital design engineer on Silicon Labs' Wireless MCU Digital Design team in Austin, TX. Day to day: designing and validating digital logic blocks for low-power wireless SoCs — RTL development, simulation and verification, debugging, and silicon bring-up. Core tech: Verilog/SystemVerilog, VLSI/digital IC design, EDA tools.
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