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VLSI Design Engineer responsible for designing cutting-edge communication systems from scratch, including micro-architecture definition, RTL coding in Verilog/SystemVerilog, synthesis, timing analysis, and PPA optimization, collaborating closely with verification, DFT, and physical design teams.
Mixed-signal engineer at NVIDIA (Bengaluru) working on a power controller: you design and enhance digital RTL (Verilog/SystemVerilog) implementing the control loop, protections, fault handling, and calibration, and build co-simulations connecting RTL with analog SPICE and Verilog-A models, debugging across the analog-digital boundary.
Designs, tests, and deploys FPGA logic on Xilinx SoC platforms for defense systems, using VHDL/Verilog and high-speed interfaces like Ethernet.
Digital Design Engineer at Anduril Industries developing FPGA and SoC platforms for high-performance embedded systems, avionics, and mission-critical hardware using RTL design in VHDL/Verilog/SystemVerilog.
Own verification of FPGA/SoC designs for flight-critical avionics using SystemVerilog and UVM methodology on AMD (Xilinx) platforms.
Senior FPGA Engineer at Anduril leading FPGA architecture, design, and verification for airborne radar systems in Colorado. Day to day: translating signal processing algorithms into high-performance FPGA implementations, establishing design processes and verification methodologies, and mentoring engineers using SystemVerilog/VHDL and Altera toolchains (Quartus/Vivado).
Senior FPGA/Digital Design Engineer on Anduril's Air Dominance and Strike team, designing and integrating RTL in VHDL/Verilog/SystemVerilog for FPGA and SoC platforms in flight-critical avionics for autonomous air vehicles. Work spans the full cycle: microarchitecture, RTL implementation, simulation, synthesis, timing closure, lab bring-up, and system integration.
Senior FPGA Verification Engineer at Anduril (Costa Mesa, CA) owns UVM-based, coverage-driven verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics. Core tech: SystemVerilog, UVM, SVA, simulators like Questa/VCS/Xcelium/Vivado, with DO-254 safety standards.
Senior firmware engineer on Anduril's Imaging team leading FPGA architecture and VHDL/Verilog design for defense imaging systems — architecting, simulating, and integrating firmware into FPGAs/SoCs, building test benches, optimizing hardware acceleration, and maturing prototypes through ground and flight testing.
Senior Embedded Engineer on Anduril's Imaging team, designing FPGA-based defense imaging systems: leading FPGA architecture, writing VHDL/Verilog for FPGAs/SoCs, integrating firmware with hardware, and validating designs with lab equipment. Onsite in Waltham, MA; U.S. Secret clearance eligibility required.
Builds and architects verification environments and testbenches for FPGA/ASIC RTL on Anduril's Imaging team — writing test plans, tracking code/functional coverage, and providing technical leadership to verification teams from prototyping through ground and flight testing. Core stack: SystemVerilog, UVM/OVM, VHDL/Verilog, Git.
Senior SoC design verification engineer developing and executing test plans, testbenches, and coverage metrics using SystemVerilog/UVM and Cadence tools (Xcelium, SimVision, Jasper), debugging RTL bugs and coordinating vendors. Remote within the US at a secure-semiconductor company serving DoD and commercial customers.
Senior Embedded Software Engineer designing and implementing embedded software for software-defined radio platforms, working with C/C++, Linux, ARM, and RF hardware on-site in Los Angeles.
Staff SoC Design Engineer at Quadric (Pune office) who owns SoC subsystem development, third-party IP integration (NoC, PCIe/UCIe, DDR, security), and PPA/timing-closure work on the company's General Purpose NPU for edge AI. Core tools: SystemVerilog/Verilog, VCS, and Verilog/C co-simulation.
Internship on Quadric's Design Verification team in Burlingame, CA, helping verify its General Purpose Neural Processing Unit (GPNPU) for edge AI devices. Day to day: documenting test plans, writing and debugging tests, and generating coverage using SystemVerilog, SystemC, or C/C++ alongside hardware architects and designers.
Builds and evolves the language, compiler, and tooling that MatX hardware engineers use daily — chiefly the open-source Bluespec compiler (Haskell) plus Rust-based hardware libraries, simulators, and design/verification flows — so architects, designers, and verification teams on the AI chip can move faster.
Staff SoC Design Engineer at Quadric, an edge-AI silicon company in downtown Burlingame, CA. You'll own SoC subsystem development and third-party IP integration (NoC, PCIe/UCIe, DDR, security), drive PPA optimization and timing closure through tapeout, and package designs for customer releases. Core stack: SystemVerilog/Verilog, VCS, Verilog/C co-simulation.
Senior SoC Design Verification Engineer at Quadric, an edge-AI processor startup: architect and build a scratch-built SoC-level UVM verification environment for GPNPU-based SoCs, develop directed/random tests, verify 3rd-party IP (NoC, PCIe/UCIe, DDR), and drive coverage using SystemVerilog/UVM, VCS, Verilog/C co-simulation, assembly, and Python.
Staff embedded software engineer at Shield AI building C/C++ avionics software for unmanned aircraft (V-BAT, X-BAT): owning features from design to production, integrating sensors, autonomy AI, firmware and ground control stations, and building CI and hardware-in-the-loop test systems.
Senior hardware engineer at Quadric (Burlingame, CA) who owns microarchitecture definition and RTL implementation of their General Purpose Neural Processing Unit in SystemC/SystemVerilog, drives PPA optimization, and carries designs through timing closure to tapeout for an edge-AI processor startup.