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VLSI Design Engineer responsible for designing cutting-edge communication systems from scratch, including micro-architecture definition, RTL coding in Verilog/SystemVerilog, synthesis, timing analysis, and PPA optimization, collaborating closely with verification, DFT, and physical design teams.
Design, implement, and verify mission-critical FPGA firmware for K2 Space's high-power satellites — owning RTL architecture in VHDL/SystemVerilog that controls propulsion, attitude control, RF, and power systems, and validating designs via simulation, bench testing, and hardware-in-the-loop testbeds.
K2 Space is hiring a Senior ASIC Design Verification Engineer to verify the functionality, performance, and robustness of custom silicon for its high-power satellites. Day to day, this means building SystemVerilog/UVM testbenches, writing assertions, running and debugging simulations, driving coverage closure, and managing regressions/CI, plus supporting silicon bring-up.
Hands-on principal-level ASIC design verification role at K2 Space, a satellite manufacturer: the engineer defines verification plans and methodology, builds SystemVerilog/UVM testbenches with assertions and coverage, manages regressions and CI, and supports silicon bring-up for custom silicon in high-power satellite platforms.
Design and verify mission-critical FPGA firmware for high-power satellites, implementing real-time control, networking, and RF systems in VHDL/SystemVerilog.
6+ month contract FPGA engineer designing and implementing digital payload code for Kepler's satellites: custom IP, DSP modulation/demodulation for on-board software-defined radios, and embedded processor/peripheral interfaces. Full FPGA flow (simulation, synthesis, place & route, timing closure, hardware testing) using Verilog/SystemVerilog/VHDL on Xilinx Zynq/UltraScale.
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RTL design engineer on AMD's Security IP (SECIP) team, designing block-level RTL and integrating embedded microprocessor subsystems and hardware accelerators (security, cryptography, compression, DMA) for AMD SoCs across client, server, graphics, and gaming. Core stack: Verilog/SystemVerilog, Python/Tcl scripting, AXI/AMBA protocols, ASIC flows.
Lead FPGA design and verification for software-defined radio platforms powering next-gen electronic warfare systems using AMD/Xilinx SOC/FPGA tools and VHDL/Verilog.
Digital Design Engineer at Anduril Industries developing FPGA and SoC platforms for high-performance embedded systems, avionics, and mission-critical hardware using RTL design in VHDL/Verilog/SystemVerilog.
Own verification of FPGA/SoC designs for flight-critical avionics using SystemVerilog and UVM methodology on AMD (Xilinx) platforms.
Senior FPGA/Digital Design Engineer on Anduril's Air Dominance and Strike team, designing and integrating RTL in VHDL/Verilog/SystemVerilog for FPGA and SoC platforms in flight-critical avionics for autonomous air vehicles. Work spans the full cycle: microarchitecture, RTL implementation, simulation, synthesis, timing closure, lab bring-up, and system integration.
Senior FPGA Verification Engineer at Anduril (Costa Mesa, CA) owns UVM-based, coverage-driven verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics. Core tech: SystemVerilog, UVM, SVA, simulators like Questa/VCS/Xcelium/Vivado, with DO-254 safety standards.
Senior/Staff FPGA Engineer on Anduril's Electronic Warfare team, owning end-to-end FPGA design and verification for software-defined radio platforms on AMD/Xilinx SoC/FPGAs — writing VHDL DSP modules, integrating subsystems, and developing drivers for custom RF boards. Core stack: VHDL/Verilog, AMD/Xilinx tools, DSP, high-speed interfaces, Linux, and Git/CI workflows.
An FPGA Engineer on Anduril's Electronic Warfare team owns end-to-end design, integration, and verification of FPGA/SoC firmware (AMD/Xilinx) for software-defined radio platforms, building VHDL DSP modules, timing/clock-domain solutions, and drivers for custom RF boards. Core stack: VHDL/Verilog, STA/CDC, Python/C/SystemVerilog testbenches, Linux, Git/CI.
Design, develop, and maintain backend Java solutions for trading systems and financial platforms built on ION technologies for a recognized financial company. Work spans analyzing business requirements, applying OOP/design patterns, TDD, DevOps/CI-CD, and Scrum with JIRA; initially remote, later based in Madrid.
Experienced FPGA developer at Kryptus, a 23-year-old Campinas-based cryptography company building HSMs, high-performance network encryptors, and quantum key distribution systems. Day to day: design RTL in SystemVerilog/VHDL for 100G/200G packet processing and hardware crypto cores (AES-256-GCM, post-quantum), close timing on AMD UltraScale+ devices, and write testbenches supporting FIPS 140-3 cert
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