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Designs and verifies FPGA hardware for onboard navigation systems in the aerospace and defence sector: defining requirements, writing VHDL, running functional simulations, and lab-testing designs. Core tech: VHDL, FPGA digital architecture design, and signal processing (FFT, filters).
qSpark is hiring a C++ developer with FPGA infrastructure experience to build and maintain low-latency, performance-critical trading infrastructure written in HLS C++ for Vivado HLS synthesis. Day to day, they write high-performance C++ for FPGA synthesis, handle lower-level FPGA code, and optimize build and synthesis environments.
The Opportunity This is a hands-on technical leadership role for an electrical engineer who still wants to be at the bench. You'll design, validate, and integrate electronic systems for complex radar and…
Build flight and ground software for spacecraft and space systems, including embedded C/VHDL and host-side GUI/database tools, to support military space missions.
Designs and tests PCBs for spacecraft and space systems, including schematics, component selection, layout, and integration, using high-speed digital, analog, RF, and low-power techniques.
Leads a geographically distributed IC design verification team at Semtech, building SystemVerilog/UVM testbenches and verification plans for mixed-signal chip blocks, driving coverage closure, regression testing, and mentoring engineers. Hybrid role in San Diego or San Jose; 10+ years of design verification experience required.
Leads and builds OPSWAT's FPGA engineering team for MetaDefender NetWall, hardware-enforced one-way security gateways for critical infrastructure and government. Owns silicon/board selection, RTL architecture, UVM verification, timing closure, and PCIe/TCP/TLS protocol termination in gateware toward 100 Gbps and NCDSMO certification.
Interns collaborate with full-time engineers on FPGA/ASIC hardware projects using OCaml and Hardcaml, from design to validation, with mentorship and exposure to Jane Street’s internal tools.
Design and implement FPGA/ASIC applications using OCaml and Hardcaml (an OCaml RTL library) for RTL design and testing, with some Verilog and C work, at a quantitative trading firm.
Designs high-speed hardware solutions (FPGAs) for ultra-low-latency trading systems, collaborating with traders and engineers to optimize network infrastructure and algorithmic trading components using VHDL/Verilog.
Applied Technical Services, LLC, is a leading provider of critical testing, inspection, certification, and compliance services. The company serves clients across a diverse set of large and stable end markets including…
This position is listed on behalf of a partner company, which manages all applications and next steps. Our partner is looking for an FPGA Digital Design Engineer based in United States. As an FPGA Digital Design…
This position is listed on behalf of a partner company, which manages all applications and next steps. Our partner is looking for an FPGA Digital Design Engineer based in Canada. As an FPGA Digital Design Engineer, you…
Designs and implements signal-processing and communications algorithms as resource-optimized RTL (VHDL/Verilog/SystemVerilog) on FPGAs for Xona's LEO PNT satellites — covering fixed-point DSP design, timing/power optimization, verification via testbenches and Python/C++ reference models, and lab/HIL bring-up.
本职位旨在领导和管理SoC的硬件原型验证平台（如基于FPGA或Emulation系统），确保为芯片系统级验证（System Validation）和早期软件开发（Software Bring-up）提供高效、稳定且功能完备的开发基座。对原型平台的资源策略、技术实现及团队能力建设负全面责任。 一、 原型资源战略规划与环境管理 1. 资源评估与基础设施建设：负责硬件原型验证资源（包括Cadence Palladium、Synopsys…
Designs and deploys FPGA-based hardware for ultra-low-latency trading at a global market maker — building systems that parse market data and execute trades in nanoseconds. Core work spans VHDL/Verilog/SystemVerilog, FPGA toolchains like Vivado and Quartus, C++/Python, and performance tuning from transceivers to logic layout.
The candidate is expected to be responsible for following tasks: Participate in complex Chip DFT/DFD feature and architecture definition Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test…
SAIC is seeking an experienced FPGA/Embedded-Systems Engineer to design, verify, and integrate advanced digital processing architectures. The ideal candidate will possess strong FPGA development experience using VHDL…
Owns the electrical and firmware architecture for Monarch Quantum's laser and photonic systems in San Diego: flowing photonic system requirements into electrical/firmware specs, designing low-noise analog signal chains, FPGA architecture, and laser-stabilization servo loops, then leading integration, hardware testing, troubleshooting, and design reviews.
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