Design Jobs in United States
There are 15,096 open Design jobs in United States on freehire right now. 3,174 of them were posted recently. The skills employers ask for most often are ai, figma and prototyping.
Salary
| Currency | Period | 25th | Median | 75th | Postings |
|---|---|---|---|---|---|
| USD | year | $126,000 | $160,000 | $199,000 | 2,023 |
| USD | hour | $26 | $35 | $60 | 181 |
From postings that disclose pay. Currencies are counted separately, never converted.
Most requested skills
- ai 27%
- figma 17%
- prototyping 13%
- photoshop 12%
- illustrator 12%
- autocad 12%
- cad 11%
- accessibility 10%
How the work is done
- Hybrid 1,976 · 13%
- Remote 1,714 · 11%
- Onsite 1,532 · 10%
Visa sponsorship offered in 29% of the 2,503 postings that state a position on it.
Seniority
- Senior 3,161
- Lead 961
- Staff 533
- Principal 484
- Intern 430
- C-level 318
Who is hiring
- 1000+ employees 2,996
- 501-1000 employees 1,324
- 51-200 employees 442
- 11-50 employees 271
- 201-500 employees 65
- 1-10 employees 18
Design Verification Engineer, Intern
Intern verifying RISC-V and AI accelerator SoCs using SystemVerilog, UVM, and Python to ensure functional correctness and robustness.
Design Verification Software Intern
Develop scalable verification infrastructure and software for high-performance RISC-V CPUs using C++, Python, and SystemVerilog. Responsibilities include building testbenches, optimizing Verilog for simulation and FPGA emulation, and maintaining CI/CD pipelines.
CPU Core Design Verification Testbench Lead
Leads verification of high-performance RISC-V CPU cores by developing and owning testbenches, debug infrastructure, and AI-assisted verification workflows.
Full-Chip Physical Design Verification Engineer
Full-chip physical design verification engineer ensuring manufacturable silicon for AI SoCs using DRC/LVS/ERC flows and advanced nodes (7nm–3nm).
SoC Physical Design Verification Engineer
Drive full-chip physical verification signoff (DRC, LVS, ERC, PERC) for advanced-node SoCs using tools like Calibre, ICV, and Pegasus, collaborating across RTL, PD, CAD, and packaging teams at an AI chip company.
Sr. Engineer, CPU RTL Design
Designs and implements RTL for high-performance RISC-V CPUs, collaborating with DV, PD, and performance teams to meet functional, timing, and power goals.
Staff Engineer, Physical Design
A Staff Engineer in Physical Design role at Tenstorrent, responsible for implementing high-performance blocks for CPU and AI/ML architectures, from synthesis to tapeout, optimizing performance, power, and area.
Staff Technical Program Manager, Physical Design
A Technical Program Manager with physical design expertise leads cross-functional teams on AI/ML and CPU processor projects, managing complex schedules and external partners for Tenstorrent's semiconductor development.
Sr. Engineer, Package Design
Senior Engineer in Package Design creates board-level routing studies, design mock-ups, and SI/PI modeling for advanced semiconductor package development using Cadence Allegro and PCB design tools.
Staff Design Verification Engineer, AI HW
Design Verification Engineer builds and runs tests for AI-native compute cores and RISC-V CPUs using SystemVerilog, Python, and CI pipelines to ensure hardware correctness before tape-out.
Physical Design Methodology Engineer, AI HW IP
Build and own RTL-to-GDSII flows for AI accelerators and CPUs, automating PPA exploration and signoff to speed IP delivery across nodes and variants.
Associate, Design - Raleigh
Designs and leads high-profile commercial workplace projects, crafts pitches to win new business, and mentors junior designers while collaborating with cross-functional teams.
Associate Design - Texas
Leads high-profile commercial workplace design projects, crafts pitches to win new business, and mentors junior designers while collaborating with cross-functional teams.