Hardware Jobs in United States
There are 3,533 open Hardware jobs in United States on freehire right now. 636 of them were posted recently. The skills employers ask for most often are ai, python and automation.
Salary
| Currency | Period | 25th | Median | 75th | Postings |
|---|---|---|---|---|---|
| USD | year | $152,650 | $185,000 | $212,785 | 850 |
| USD | hour | $28 | $40 | $48 | 35 |
From postings that disclose pay. Currencies are counted separately, never converted.
Most requested skills
- ai 34%
- python 28%
- automation 20%
- fpga 18%
- verilog 17%
- networking 15%
- ethernet 14%
- assembly 13%
How the work is done
- Onsite 685 · 19%
- Hybrid 290 · 8%
- Remote 115 · 3%
Visa sponsorship offered in 45% of the 1,009 postings that state a position on it.
Seniority
- Senior 752
- Principal 273
- Staff 201
- Lead 194
- Intern 135
- C-level 53
Who is hiring
- 1000+ employees 1,162
- 501-1000 employees 243
- 11-50 employees 108
- 51-200 employees 89
- 201-500 employees 13
- 1-10 employees 9
Physical Design Engineer
Designs and implements high-performance CPU and AI/ML chip blocks from synthesis to tapeout, optimizing power, performance, and area using advanced EDA tools and methodologies.
Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
Physical Design Engineer owning Die-to-Die interface implementation from RTL to GDSII for advanced-node chiplet architectures, using full PD flow (synthesis, P&R, CTS, sign-off) with Synopsys/Cadence/Mentor EDA tools and Tcl/Python automation.
Physical Design Engineer, PnR
Designs and implements high-performance AI SoC partitions from synthesis to tapeout, focusing on timing, power intent, and physical verification using Synopsys tools (Design Compiler, Fusion Compiler, IC Compiler II).
Physical Design Engineer - STA
Drive static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs, collaborating with logic, DFT, and physical design teams using STA tools, SDC constraints, and Python/Perl/TCL scripting.
Sr. Engineer, SoC Design Verification
Designs and runs pre-silicon verification for debug/test logic in AI SoCs using UVM, Siemens Tessent, and JTAG flows to ensure silicon bring-up succeeds.
Staff Physical Design Engineer
Implement physical design for RISC-V CPUs and AI architectures, owning the flow from synthesis to tapeout to optimize performance, power, and area.
Top Level Physical Design Engineer
Designs and implements high-performance AI and CPU System-on-Chip layouts, optimizing power, performance, and area while collaborating with architecture and packaging teams.
System Hardware Technician
Maintain and troubleshoot cutting-edge AI hardware systems in R&D labs and data centers, supporting servers, PCIe devices, and prototype platforms for next-gen compute.
PCB Layout Engineer
Designs and routes high-speed, multi-layer PCBs for AI and high-performance computing hardware, using Cadence Allegro and collaborating with cross-functional teams to meet strict signal integrity and manufacturing requirements.
Physical Design Engineer, AI Accelerator IP
Owns end-to-end physical design of AI accelerator IP blocks, from synthesis to GDSII signoff, ensuring PPA targets and customer timelines are met.
FPGA Engineer
Designs and implements FPGA/RTL logic for satellite compute payloads, including sensor interfaces, DDR/DMA datapaths, and ARM SoC integration, to support orbital data and energy systems.
Manufacturing Quality Engineer- Hardware Development
Specialist designs and validates Point-of-Sale hardware staging processes, creates Bills of Materials, and ensures packaging meets retail customer requirements.
Vice President of Hardware Development
Leads global teams to design, build, and deploy enterprise retail hardware platforms, intelligent peripherals, and cloud-connected device management systems using Linux, edge computing, and AI.
Hardware Systems Design Engineer - Circuit Board
Senior electrical engineer designing and debugging cloud compute server systems and PCB boards, leading architecture, schematics, and bring-up while balancing cost, performance, and schedule.
Senior Manager Engineering - Hardware
Leads a 24-person hardware engineering team at Toshiba Global Commerce Solutions, overseeing retail POS hardware development, architecture, and operational excellence in Durham, NC.